Program 2: Arithmetic, logic, shifts, and comparisons

Program catalogue · Instruction reference · Executable reference

Purpose

Exercise register and immediate ALU instructions, signed/unsigned comparisons, and writes to x0; preserve the results in data memory.

This is an instruction-behavior correctness fixture.

Setup

Property	Value
Benchmark workload ID	program-02
Headless selection	--program 2
Visualizer scenario	rv32i-program2
Registered test	RV32ISingleCycleSystemTest/program-02
Instruction image	35 words, starting at 0x00000000; last word at 0x00000088
Initial state	PC = 0x00000000; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
x1	Operand 0x55 (85)
x2	Operand 0x0F (15)
x10	Signed operand -8
x3–x9, x11–x17	Operation results
x20	Output base at 0x200
x0	Attempted destination that must remain zero

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

addi x1, x0, 85                # 0x00000000 | 0x05500093
addi x2, x0, 15                # 0x00000004 | 0x00F00113
addi x10, x0, -8               # 0x00000008 | 0xFF800513
add x3, x1, x2                 # 0x0000000C | 0x002081B3
sub x4, x1, x2                 # 0x00000010 | 0x40208233
and x5, x1, x2                 # 0x00000014 | 0x0020F2B3
or x6, x1, x2                  # 0x00000018 | 0x0020E333
xor x7, x1, x2                 # 0x0000001C | 0x0020C3B3
slli x8, x2, 4                 # 0x00000020 | 0x00411413
srli x9, x8, 2                 # 0x00000024 | 0x00245493
srai x11, x10, 1               # 0x00000028 | 0x40155593
slt x12, x10, x1               # 0x0000002C | 0x00152633
sltu x13, x10, x1              # 0x00000030 | 0x001536B3
xori x14, x1, 51               # 0x00000034 | 0x0330C713
ori x14, x14, 256              # 0x00000038 | 0x10076713
andi x15, x1, 63               # 0x0000003C | 0x03F0F793
slti x16, x10, 0               # 0x00000040 | 0x00052813
sltiu x17, x10, 1              # 0x00000044 | 0x00153893
addi x0, x0, 123               # 0x00000048 | 0x07B00013
addi x20, x0, 0x200            # 0x0000004C | 0x20000A13
sw x3, 0(x20)                  # 0x00000050 | 0x003A2023
sw x4, 4(x20)                  # 0x00000054 | 0x004A2223
sw x5, 8(x20)                  # 0x00000058 | 0x005A2423
sw x6, 12(x20)                 # 0x0000005C | 0x006A2623
sw x7, 16(x20)                 # 0x00000060 | 0x007A2823
sw x8, 20(x20)                 # 0x00000064 | 0x008A2A23
sw x9, 24(x20)                 # 0x00000068 | 0x009A2C23
sw x11, 28(x20)                # 0x0000006C | 0x00BA2E23
sw x12, 32(x20)                # 0x00000070 | 0x02CA2023
sw x13, 36(x20)                # 0x00000074 | 0x02DA2223
sw x14, 40(x20)                # 0x00000078 | 0x02EA2423
sw x15, 44(x20)                # 0x0000007C | 0x02FA2623
sw x16, 48(x20)                # 0x00000080 | 0x030A2823
sw x17, 52(x20)                # 0x00000084 | 0x031A2A23
ebreak                         # 0x00000088 | 0x00100073

Execution

1. Initialize x1=0x55, x2=0x0F, and x10=-8.
2. Compute addition, subtraction, bitwise operations, shifts, and comparisons into separate registers. Logical right shift inserts zero bits; arithmetic right shift preserves the sign of -8, producing -4.
3. Signed comparisons interpret -8 as negative; unsigned comparisons interpret the same bits as 0xFFFFFFF8. Thus SLT/SLTI produce 1 while the corresponding unsigned tests produce 0.
4. Attempt addi x0, x0, 123; x0 remains zero. Store fourteen result words consecutively at 0x200–0x234, then halt.

The stored words, in order, are 0x64, 0x46, 0x05, 0x5F, 0x5A, 0xF0, 0x3C, 0xFFFFFFFC, 1, 0, 0x166, 0x15, 1, 0. All 35 instructions execute once.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
x0	0x00000000	Attempted destination that must remain zero
x3	0x00000064	Register result
x4	0x00000046	Register result
x8	0x000000F0	Register result
x9	0x0000003C	Register result
x11	0xFFFFFFFC	Register result
x12	0x00000001	Register result
x13	0x00000000	Register result
x14	0x00000166	Register result
x15	0x00000015	Register result
x16	0x00000001	Register result
x17	0x00000000	Register result
PC	0x00000088	EBREAK address
Attempts	35	Checkpoints I0–I34
HALTED	1	Project halt
TRAPPED	0	No exception
TRAP_CAUSE	0	None, a project enum code

Start address	Bytes, in increasing address order
0x00000200	64 00 00 00
0x00000204	46 00 00 00
0x00000208	05 00 00 00
0x0000020C	5F 00 00 00
0x00000210	5A 00 00 00
0x00000214	F0 00 00 00
0x00000218	3C 00 00 00
0x0000021C	FC FF FF FF
0x00000220	01 00 00 00
0x00000224	00 00 00 00
0x00000228	66 01 00 00
0x0000022C	15 00 00 00
0x00000230	01 00 00 00
0x00000234	00 00 00 00

All data bytes not listed as written retain their initial values. The output region contains fourteen little-endian words. Some registers holding intermediate operands/results are intentionally absent from the fixture's selected-register assertions.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 2 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 35 instruction attempts are included, with absolute simulator time and checkpoint number. The terminating EBREAK is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 35 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-02, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7080	ADDI @ 0x00000000	raw=0x05500093, pc_after=0x00000004, wb=x1=0x00000055, mem=None, flow=next
I1	11080	ADDI @ 0x00000004	raw=0x00f00113, pc_after=0x00000008, wb=x2=0x0000000f, mem=None, flow=next
I2	15080	ADDI @ 0x00000008	raw=0xff800513, pc_after=0x0000000c, wb=x10=0xfffffff8, mem=None, flow=next
I3	19080	ADD @ 0x0000000c	raw=0x002081b3, pc_after=0x00000010, wb=x3=0x00000064, mem=None, flow=next
I4	23080	SUB @ 0x00000010	raw=0x40208233, pc_after=0x00000014, wb=x4=0x00000046, mem=None, flow=next
I5	27080	AND @ 0x00000014	raw=0x0020f2b3, pc_after=0x00000018, wb=x5=0x00000005, mem=None, flow=next
I6	31080	OR @ 0x00000018	raw=0x0020e333, pc_after=0x0000001c, wb=x6=0x0000005f, mem=None, flow=next
I7	35080	XOR @ 0x0000001c	raw=0x0020c3b3, pc_after=0x00000020, wb=x7=0x0000005a, mem=None, flow=next
I8	39080	SLLI @ 0x00000020	raw=0x00411413, pc_after=0x00000024, wb=x8=0x000000f0, mem=None, flow=next
I9	43080	SRLI @ 0x00000024	raw=0x00245493, pc_after=0x00000028, wb=x9=0x0000003c, mem=None, flow=next
I10	47080	SRAI @ 0x00000028	raw=0x40155593, pc_after=0x0000002c, wb=x11=0xfffffffc, mem=None, flow=next
I11	51080	SLT @ 0x0000002c	raw=0x00152633, pc_after=0x00000030, wb=x12=0x00000001, mem=None, flow=next
I12	55080	SLTU @ 0x00000030	raw=0x001536b3, pc_after=0x00000034, wb=x13=0x00000000, mem=None, flow=next
I13	59080	XORI @ 0x00000034	raw=0x0330c713, pc_after=0x00000038, wb=x14=0x00000066, mem=None, flow=next
I14	63080	ORI @ 0x00000038	raw=0x10076713, pc_after=0x0000003c, wb=x14=0x00000166, mem=None, flow=next
I15	67080	ANDI @ 0x0000003c	raw=0x03f0f793, pc_after=0x00000040, wb=x15=0x00000015, mem=None, flow=next
I16	71080	SLTI @ 0x00000040	raw=0x00052813, pc_after=0x00000044, wb=x16=0x00000001, mem=None, flow=next
I17	75080	SLTIU @ 0x00000044	raw=0x00153893, pc_after=0x00000048, wb=x17=0x00000000, mem=None, flow=next
I18	79080	ADDI @ 0x00000048	raw=0x07b00013, pc_after=0x0000004c, wb=x0=0x0000007b ignored-x0, mem=None, flow=next
I19	83080	ADDI @ 0x0000004c	raw=0x20000a13, pc_after=0x00000050, wb=x20=0x00000200, mem=None, flow=next
I20	87080	SW @ 0x00000050	raw=0x003a2023, pc_after=0x00000054, wb=None, mem=Write Word @0x00000200 <- 0x00000064, flow=next
I21	91080	SW @ 0x00000054	raw=0x004a2223, pc_after=0x00000058, wb=None, mem=Write Word @0x00000204 <- 0x00000046, flow=next
I22	95080	SW @ 0x00000058	raw=0x005a2423, pc_after=0x0000005c, wb=None, mem=Write Word @0x00000208 <- 0x00000005, flow=next
I23	99080	SW @ 0x0000005c	raw=0x006a2623, pc_after=0x00000060, wb=None, mem=Write Word @0x0000020c <- 0x0000005f, flow=next
I24	103080	SW @ 0x00000060	raw=0x007a2823, pc_after=0x00000064, wb=None, mem=Write Word @0x00000210 <- 0x0000005a, flow=next
I25	107080	SW @ 0x00000064	raw=0x008a2a23, pc_after=0x00000068, wb=None, mem=Write Word @0x00000214 <- 0x000000f0, flow=next
I26	111080	SW @ 0x00000068	raw=0x009a2c23, pc_after=0x0000006c, wb=None, mem=Write Word @0x00000218 <- 0x0000003c, flow=next
I27	115080	SW @ 0x0000006c	raw=0x00ba2e23, pc_after=0x00000070, wb=None, mem=Write Word @0x0000021c <- 0xfffffffc, flow=next
I28	119080	SW @ 0x00000070	raw=0x02ca2023, pc_after=0x00000074, wb=None, mem=Write Word @0x00000220 <- 0x00000001, flow=next
I29	123080	SW @ 0x00000074	raw=0x02da2223, pc_after=0x00000078, wb=None, mem=Write Word @0x00000224 <- 0x00000000, flow=next
I30	127080	SW @ 0x00000078	raw=0x02ea2423, pc_after=0x0000007c, wb=None, mem=Write Word @0x00000228 <- 0x00000166, flow=next
I31	131080	SW @ 0x0000007c	raw=0x02fa2623, pc_after=0x00000080, wb=None, mem=Write Word @0x0000022c <- 0x00000015, flow=next
I32	135080	SW @ 0x00000080	raw=0x030a2823, pc_after=0x00000084, wb=None, mem=Write Word @0x00000230 <- 0x00000001, flow=next
I33	139080	SW @ 0x00000084	raw=0x031a2a23, pc_after=0x00000088, wb=None, mem=Write Word @0x00000234 <- 0x00000000, flow=next
I34	143080	EBREAK @ 0x00000088	raw=0x00100073, pc_after=0x00000088, wb=None, mem=None, flow=next, halted=true

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