Program 11: Misaligned word load

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Purpose

Reject a word load from an accessible but non-word-aligned address.

This is a negative test: the named trap is the expected outcome, not a failed simulation.

Setup

Property	Value
Benchmark workload ID	program-11
Headless selection	--program 11
Visualizer scenario	rv32i-program11
Registered test	RV32ISingleCycleSystemTest/program-11
Instruction image	3 words, starting at 0x00000000; last word at 0x00000008
Initial state	PC = 0x00000000; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
x1	Address 0x101
x2	Faulting load destination; remains zero

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

addi x1, x0, 0x101             # 0x00000000 | 0x10100093
lw x2, 0(x1)                   # 0x00000004 | 0x0000A103
ebreak                         # 0x00000008 | 0x00100073

Execution

1. ADDI sets x1=0x101, an address inside data memory.
2. LW at 0x04 requests four bytes from that address. Since 0x101 % 4 != 0, the load produces LoadAddressMisaligned before a destination write.
3. PC remains 0x04, x2 stays zero, and the following EBREAK does not execute. Two attempts occur.

Zero-filled memory does not turn this into a successful zero-valued load: alignment is checked first.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
x1	0x00000101	Address 0x101
x2	0x00000000	Faulting load destination; remains zero
PC	0x00000004	Faulting attempt address
Attempts	2	Checkpoints I0–I1
HALTED	0	No EBREAK halt
TRAPPED	1	Expected terminal exception
TRAP_CAUSE	5	LoadAddressMisaligned, a project enum code

Start address	Bytes, in increasing address order
None	—

No data writes occur; the initial data image is unchanged. This isolates alignment, not capacity: the address range itself is available.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 11 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 2 instruction attempts are included, with absolute simulator time and checkpoint number. The terminal fault is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 2 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-11, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7080	ADDI @ 0x00000000	raw=0x10100093, pc_after=0x00000004, wb=x1=0x00000101, mem=None, flow=next
I1	11080	LW @ 0x00000004	raw=0x0000a103, pc_after=0x00000004, wb=None, mem=Read Word @0x00000101 -> 0x00000000 fault, flow=next, trapped=true cause=LoadAddressMisaligned

Open program 11 reference