§ 4.3.5. Memory Access

These are CPU-side components. The lane/alignment logic is shared by both cores. The pipeline additionally uses a requester to hold one universal memory transaction until completion; the strict single-cycle and baseline cores use zero-wait endpoint pins with combinational port formatting, not a stateful requester. These components do not contain storage or replace a technology-specific controller.

Component	Description	Structural	Behavioral
RV32IMemoryLanes	Little-endian subword extraction, store placement, masks, and endpoint address	Yes	Yes
RV32IMemoryAlignmentUnit	Address alignment predicate	Yes	Yes
RV32IMemoryRequest	CPU-owned, one-outstanding transaction requester	Yes	Yes

Columns count registered implementations. Behavioral pipeline cores contain equivalent requester bookkeeping; the single-cycle Memory stage contains only equivalent formatting logic. Those helpers are not separately selectable implementations of these building blocks. C++ examples below specify binary behavior without propagation delays.

Pipeline transaction path. Lanes = RV32IMemoryLanes; Request = RV32IMemoryRequest. Endpoint = controller plus native storage, or its fused MemoryEndpoint. The single-cycle and baseline cores re-use Lanes with combinational formatting to zero-wait endpoints. Arrows show payload flow, not clock cycles or the complete handshake wiring.

The two rows separate outgoing payloads from returning data; they do not duplicate hardware. Request/response handshakes and CPU-side issue, completion, and fault controls are specified in the pin tables below.

4.3.5.1. RV32IMemoryLanes

IO pins

Pin	Direction	Width	Description
ADDR	Input	32	CPU byte address
WRITE_DATA	Input	32	Unshifted store source register
WORD_DATA	Input	32	Complete word returned by the endpoint
SIZE	Input	2	0: byte; 1: halfword; 2: word; 3: invalid
SIGN_EXTEND	Input	1	Sign-extend byte/halfword loads
WORD_ADDR	Output	32	Endpoint byte address, not a word index
WORD_WRITE_DATA	Output	32	Store data shifted to its byte lane
READ_DATA	Output	32	CPU load result
WRITE_MASK	Output	4	One enable per endpoint byte lane

Behavior

Offset is ADDR[1:0]. Byte lane 0 is bits 7:0; lane 3 is bits 31:24. Valid accesses use WORD_ADDR = ADDR & ~3. Byte stores enable one lane; aligned halfword stores enable lanes 0–1 or 2–3; word stores enable all four. Store data moves left by offset*8; load data moves right by that amount, then is narrowed and sign/zero-extended.

A halfword at an odd address, word at a nonzero offset, or SIZE=3 must not silently become an aligned legal access. The output address therefore sets bit 0 on these cases, making the endpoint reject the request as unaligned. There is no split transaction across words. Invalid inputs still produce deterministic combinational data/masks, but these are not permission to write: the endpoint must reject the bad address. SIZE=3 gives read data and mask zero.

C++ example

#include <cstdint>
namespace memory_access_example {
struct Lanes { uint32_t WORD_ADDR, WORD_WRITE_DATA, READ_DATA; unsigned WRITE_MASK; };
Lanes lanes(uint32_t address, uint32_t write, uint32_t word, unsigned size, bool sign) {
    const unsigned offset=address&3;
    const bool bad=size==3 || (size==1 && (offset&1)) || (size==2 && offset!=0);
    const uint32_t shifted=word>>(8*offset);
    uint32_t read=size==0 ? shifted&255 : size==1 ? shifted&65535 : size==2 ? shifted : 0;
    if (sign && size==0 && (read&128)) read|=0xffffff00U;
    if (sign && size==1 && (read&32768)) read|=0xffff0000U;
    const unsigned mask=size==0 ? 1U<<offset : size==1 ? 3U<<(offset&2) : size==2 ? 15 : 0;
    return {(address&~uint32_t{3})|uint32_t(bad),write<<(8*offset),read,mask};
}
}

Unknown inputs and timing

This is a combinational structural network. Splitters and rewires preserve individual X/Z bits; muxes and sign-extension gates can mask or propagate them. A known size or disabled sign extension may isolate unrelated bits. The binary example does not model those cases or the different path delays.

Implementation

Structural implementation

Nine top-level children expose the data flow instead of placing every bit gate side by side:

Child	Structural helper / responsibility
ADDRESS	RV32IMemoryAddress: address/size decoding, guarded word address, byte offset, byte/halfword/word enables
LANE_0 … LANE_3	Rewire four possible byte placements for store and load data
STORE_LANES, LOAD_LANES	Select the requested byte offset
LOAD_EXTEND	RV32ILoadExtender: select byte/halfword/word data and sign/zero extension
WRITE_MASK	RV32IByteWriteMask: generate the four byte-write enables

ADDRESS receives ADDR[32] and SIZE[2]; it outputs WORD_ADDR[32], OFFSET[2], and BYTE/HALF/WORD. LOAD_EXTEND receives shifted DATA[32], those three enables, and SIGN_EXTEND; its OUT[32] is assembled from four RV32ILoadByte<0…3> circuits. Each byte circuit contains eight numbered bit lanes; lower bytes retain input bits while higher bytes select the relevant sign fill. WRITE_MASK receives the offset and size enables and produces MASK[4].

The internal helpers are fixed structural parts with no state and no behavioral variants of their own; grouping does not turn them into behavioral memory devices.

Behavioral implementation

RV32IMemoryLanesBehavioral computes the four outputs with the same lane functions the behavioral cores call (memoryWordAddress, memoryLoadData, memoryWriteMask, and the store shift), with gate-derived output timing when selected through the catalog. It is defined for known binary inputs: if any input bit is X or Z, every output is unknown. Partial-unknown behavior is specified by the structural gates only.

Examples

All 32 recorded rows of RV32IMemoryLanesTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (855fad65681ed169). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	ADDRInput · 32 bit	SIGN_EXTENDInput · 1 bit	SIZEInput · 2 bit	WORD_DATAInput · 32 bit	WRITE_DATAInput · 32 bit	READ_DATAExpected output · 32 bit	WORD_ADDRExpected output · 32 bit	WORD_WRITE_DATAExpected output · 32 bit	WRITE_MASKExpected output · 4 bit
#0size-0-lane-0-sign-0	11	0x00000100	0	0x0	0x80FF3412	0xDEADBEEF	0x00000012	0x00000100	0xDEADBEEF	0x1
#1size-0-lane-0-sign-1	13	0x00000100	1	0x0	0x80FF3412	0xDEADBEEF	0x00000012	0x00000100	0xDEADBEEF	0x1
#2size-0-lane-1-sign-0	25	0x00000101	0	0x0	0x80FF3412	0xDEADBEEF	0x00000034	0x00000100	0xADBEEF00	0x2
#3size-0-lane-1-sign-1	28	0x00000101	1	0x0	0x80FF3412	0xDEADBEEF	0x00000034	0x00000100	0xADBEEF00	0x2
#4size-0-lane-2-sign-0	40	0x00000102	0	0x0	0x80FF3412	0xDEADBEEF	0x000000FF	0x00000100	0xBEEF0000	0x4
#5size-0-lane-2-sign-1	45	0x00000102	1	0x0	0x80FF3412	0xDEADBEEF	0xFFFFFFFF	0x00000100	0xBEEF0000	0x4
#6size-0-lane-3-sign-0	57	0x00000103	0	0x0	0x80FF3412	0xDEADBEEF	0x00000080	0x00000100	0xEF000000	0x8
#7size-0-lane-3-sign-1	62	0x00000103	1	0x0	0x80FF3412	0xDEADBEEF	0xFFFFFF80	0x00000100	0xEF000000	0x8
#8size-1-lane-0-sign-0	74	0x00000100	0	0x1	0x80FF3412	0xDEADBEEF	0x00003412	0x00000100	0xDEADBEEF	0x3
#9size-1-lane-0-sign-1	76	0x00000100	1	0x1	0x80FF3412	0xDEADBEEF	0x00003412	0x00000100	0xDEADBEEF	0x3
#10size-1-lane-1-sign-0	88	0x00000101	0	0x1	0x80FF3412	0xDEADBEEF	0x0000FF34	0x00000101	0xADBEEF00	0x3
#11size-1-lane-1-sign-1	93	0x00000101	1	0x1	0x80FF3412	0xDEADBEEF	0xFFFFFF34	0x00000101	0xADBEEF00	0x3
#12size-1-lane-2-sign-0	105	0x00000102	0	0x1	0x80FF3412	0xDEADBEEF	0x000080FF	0x00000100	0xBEEF0000	0xC
#13size-1-lane-2-sign-1	110	0x00000102	1	0x1	0x80FF3412	0xDEADBEEF	0xFFFF80FF	0x00000100	0xBEEF0000	0xC
#14size-1-lane-3-sign-0	122	0x00000103	0	0x1	0x80FF3412	0xDEADBEEF	0x00000080	0x00000101	0xEF000000	0xC
#15size-1-lane-3-sign-1	125	0x00000103	1	0x1	0x80FF3412	0xDEADBEEF	0x00000080	0x00000101	0xEF000000	0xC
#16size-2-lane-0-sign-0	136	0x00000100	0	0x2	0x80FF3412	0xDEADBEEF	0x80FF3412	0x00000100	0xDEADBEEF	0xF
#17size-2-lane-0-sign-1	138	0x00000100	1	0x2	0x80FF3412	0xDEADBEEF	0x80FF3412	0x00000100	0xDEADBEEF	0xF
#18size-2-lane-1-sign-0	149	0x00000101	0	0x2	0x80FF3412	0xDEADBEEF	0x0080FF34	0x00000101	0xADBEEF00	0xF
#19size-2-lane-1-sign-1	152	0x00000101	1	0x2	0x80FF3412	0xDEADBEEF	0x0080FF34	0x00000101	0xADBEEF00	0xF
#20size-2-lane-2-sign-0	163	0x00000102	0	0x2	0x80FF3412	0xDEADBEEF	0x000080FF	0x00000101	0xBEEF0000	0xF
#21size-2-lane-2-sign-1	166	0x00000102	1	0x2	0x80FF3412	0xDEADBEEF	0x000080FF	0x00000101	0xBEEF0000	0xF
#22size-2-lane-3-sign-0	177	0x00000103	0	0x2	0x80FF3412	0xDEADBEEF	0x00000080	0x00000101	0xEF000000	0xF
#23size-2-lane-3-sign-1	180	0x00000103	1	0x2	0x80FF3412	0xDEADBEEF	0x00000080	0x00000101	0xEF000000	0xF
#24size-3-lane-0-sign-0	190	0x00000100	0	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xDEADBEEF	0x0
#25size-3-lane-0-sign-1	192	0x00000100	1	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xDEADBEEF	0x0
#26size-3-lane-1-sign-0	202	0x00000101	0	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xADBEEF00	0x0
#27size-3-lane-1-sign-1	205	0x00000101	1	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xADBEEF00	0x0
#28size-3-lane-2-sign-0	215	0x00000102	0	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xBEEF0000	0x0
#29size-3-lane-2-sign-1	218	0x00000102	1	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xBEEF0000	0x0
#30size-3-lane-3-sign-0	228	0x00000103	0	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xEF000000	0x0
#31size-3-lane-3-sign-1	231	0x00000103	1	0x3	0x80FF3412	0xDEADBEEF	0x00000000	0x00000101	0xEF000000	0x0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open memory lanes

Tests

RV32IMemoryLanesTest exposes 32 checkpoints covering all four size encodings, four offsets, and both sign modes. RV32IMemoryMigrationTest additionally exercises formatting against real endpoint responses and checks that rejected stores do not change storage. These are sampled data words, not an exhaustive 32-bit operand test.

4.3.5.2. RV32IMemoryAlignmentUnit

IO pins

Pin	Direction	Width	Description
ADDRESS	Input	32	CPU byte address
SIZE	Input	2	Access-size encoding
MISALIGNED	Output	1	Address violates the selected alignment

Behavior

Byte accesses accept every address; halfwords require bit 0 zero; words require bits 1:0 zero. The circuit equation is SIZE[0]·ADDRESS[0] OR SIZE[1]·(ADDRESS[0] OR ADDRESS[1]). Consequently reserved SIZE=3 has the same alignment predicate as word accesses; an aligned address produces zero. This component is not a size-validity checker. The lane formatter and execution-status unit separately reject size 3.

The single-cycle Memory stage also adds a size-3 check to its public MISALIGNED output. Fetch and Next PC use this building block with constant word size.

C++ example

namespace memory_access_example {
bool misaligned(uint32_t address, unsigned size) {
    return ((size&1) && (address&1)) || ((size&2) && (address&3));
}
}

Unknown inputs and timing

Only the low two address bits and both size bits matter. AND with zero and OR with one mask unknowns; other indeterminate gate results become X. Both implementations use that equation, including SIZE=3 and X/Z. The registered behavioral checker uses gate-derived per-path delays; structural timing follows its individual gates.

Implementation

Structural implementation

Two splitters, two AND gates, and two OR gates evaluate the predicate. It is registered as rv32i.pipeline.memory-alignment, but its address check is not intrinsically pipeline-specific.

Behavioral implementation

RV32IMemoryAlignmentBehavioral evaluates the same four-state gate expression without internal components. It does not coerce unknown bits into a binary integer.

Examples

All 262 recorded rows of RV32IMemoryAlignmentUnitTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: rv32i-component-preview-preview / structural (4a6379727cf50a7a). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	ADDRESSInput · 32 bit	SIZEInput · 2 bit	MISALIGNEDExpected output · 1 bit
#0byte-any-address	3	0x00000103	0x0	0
#1aligned-halfword	6	0x00000102	0x1	0
#2misaligned-halfword	10	0x00000103	0x1	1
#3aligned-word	15	0x00000104	0x2	0
#4word-offset-one	20	0x00000105	0x2	1
#5word-offset-two	23	0x00000106	0x2	1
#6four-state-0	27	0x00000100	0x0	0
#7four-state-1	31	0x00000101	0x0	0
#8four-state-2	35	0b0000000000000000000000010000000X	0x0	0
#9four-state-3	38	0b0000000000000000000000010000000Z	0x0	0
#10four-state-4	42	0x00000102	0x0	0
#11four-state-5	45	0x00000103	0x0	0
#12four-state-6	48	0b0000000000000000000000010000001X	0x0	0
#13four-state-7	51	0b0000000000000000000000010000001Z	0x0	0
#14four-state-8	55	0b000000000000000000000001000000X0	0x0	0
#15four-state-9	59	0b000000000000000000000001000000X1	0x0	0
#16four-state-10	63	0b000000000000000000000001000000XX	0x0	0
#17four-state-11	66	0b000000000000000000000001000000XZ	0x0	0
#18four-state-12	69	0b000000000000000000000001000000Z0	0x0	0
#19four-state-13	73	0b000000000000000000000001000000Z1	0x0	0
#20four-state-14	77	0b000000000000000000000001000000ZX	0x0	0
#21four-state-15	80	0b000000000000000000000001000000ZZ	0x0	0
#22four-state-16	84	0x00000100	0x1	0
#23four-state-17	88	0x00000101	0x1	1
#24four-state-18	92	0b0000000000000000000000010000000X	0x1	X
#25four-state-19	95	0b0000000000000000000000010000000Z	0x1	X
#26four-state-20	99	0x00000102	0x1	0
#27four-state-21	103	0x00000103	0x1	1
#28four-state-22	107	0b0000000000000000000000010000001X	0x1	X
#29four-state-23	110	0b0000000000000000000000010000001Z	0x1	X
#30four-state-24	114	0b000000000000000000000001000000X0	0x1	0
#31four-state-25	118	0b000000000000000000000001000000X1	0x1	1
#32four-state-26	122	0b000000000000000000000001000000XX	0x1	X
#33four-state-27	125	0b000000000000000000000001000000XZ	0x1	X
#34four-state-28	129	0b000000000000000000000001000000Z0	0x1	0
#35four-state-29	133	0b000000000000000000000001000000Z1	0x1	1
#36four-state-30	137	0b000000000000000000000001000000ZX	0x1	X
#37four-state-31	140	0b000000000000000000000001000000ZZ	0x1	X
#38four-state-32	144	0x00000100	0b0X	0
#39four-state-33	148	0x00000101	0b0X	X
#40four-state-34	152	0b0000000000000000000000010000000X	0b0X	X
#41four-state-35	155	0b0000000000000000000000010000000Z	0b0X	X
#42four-state-36	159	0x00000102	0b0X	0
#43four-state-37	163	0x00000103	0b0X	X
#44four-state-38	166	0b0000000000000000000000010000001X	0b0X	X
#45four-state-39	169	0b0000000000000000000000010000001Z	0b0X	X
#46four-state-40	173	0b000000000000000000000001000000X0	0b0X	0
#47four-state-41	177	0b000000000000000000000001000000X1	0b0X	X
#48four-state-42	181	0b000000000000000000000001000000XX	0b0X	X
#49four-state-43	184	0b000000000000000000000001000000XZ	0b0X	X
#50four-state-44	188	0b000000000000000000000001000000Z0	0b0X	0
#51four-state-45	192	0b000000000000000000000001000000Z1	0b0X	X
#52four-state-46	196	0b000000000000000000000001000000ZX	0b0X	X
#53four-state-47	199	0b000000000000000000000001000000ZZ	0b0X	X
#54four-state-48	203	0x00000100	0b0Z	0
#55four-state-49	207	0x00000101	0b0Z	X
#56four-state-50	211	0b0000000000000000000000010000000X	0b0Z	X
#57four-state-51	214	0b0000000000000000000000010000000Z	0b0Z	X
#58four-state-52	218	0x00000102	0b0Z	0
#59four-state-53	222	0x00000103	0b0Z	X
#60four-state-54	225	0b0000000000000000000000010000001X	0b0Z	X
#61four-state-55	228	0b0000000000000000000000010000001Z	0b0Z	X
#62four-state-56	232	0b000000000000000000000001000000X0	0b0Z	0
#63four-state-57	236	0b000000000000000000000001000000X1	0b0Z	X
#64four-state-58	240	0b000000000000000000000001000000XX	0b0Z	X
#65four-state-59	243	0b000000000000000000000001000000XZ	0b0Z	X
#66four-state-60	247	0b000000000000000000000001000000Z0	0b0Z	0
#67four-state-61	251	0b000000000000000000000001000000Z1	0b0Z	X
#68four-state-62	255	0b000000000000000000000001000000ZX	0b0Z	X
#69four-state-63	258	0b000000000000000000000001000000ZZ	0b0Z	X
#70four-state-64	263	0x00000100	0x2	0
#71four-state-65	268	0x00000101	0x2	1
#72four-state-66	273	0b0000000000000000000000010000000X	0x2	X
#73four-state-67	276	0b0000000000000000000000010000000Z	0x2	X
#74four-state-68	281	0x00000102	0x2	1
#75four-state-69	284	0x00000103	0x2	1
#76four-state-70	287	0b0000000000000000000000010000001X	0x2	1
#77four-state-71	290	0b0000000000000000000000010000001Z	0x2	1
#78four-state-72	295	0b000000000000000000000001000000X0	0x2	X
#79four-state-73	300	0b000000000000000000000001000000X1	0x2	1
#80four-state-74	305	0b000000000000000000000001000000XX	0x2	X
#81four-state-75	308	0b000000000000000000000001000000XZ	0x2	X
#82four-state-76	311	0b000000000000000000000001000000Z0	0x2	X
#83four-state-77	316	0b000000000000000000000001000000Z1	0x2	1
#84four-state-78	321	0b000000000000000000000001000000ZX	0x2	X
#85four-state-79	324	0b000000000000000000000001000000ZZ	0x2	X
#86four-state-80	329	0x00000100	0x3	0
#87four-state-81	334	0x00000101	0x3	1
#88four-state-82	339	0b0000000000000000000000010000000X	0x3	X
#89four-state-83	342	0b0000000000000000000000010000000Z	0x3	X
#90four-state-84	347	0x00000102	0x3	1
#91four-state-85	351	0x00000103	0x3	1
#92four-state-86	355	0b0000000000000000000000010000001X	0x3	1
#93four-state-87	358	0b0000000000000000000000010000001Z	0x3	1
#94four-state-88	363	0b000000000000000000000001000000X0	0x3	X
#95four-state-89	368	0b000000000000000000000001000000X1	0x3	1
#96four-state-90	373	0b000000000000000000000001000000XX	0x3	X
#97four-state-91	376	0b000000000000000000000001000000XZ	0x3	X
#98four-state-92	380	0b000000000000000000000001000000Z0	0x3	X
#99four-state-93	385	0b000000000000000000000001000000Z1	0x3	1
#100four-state-94	390	0b000000000000000000000001000000ZX	0x3	X
#101four-state-95	393	0b000000000000000000000001000000ZZ	0x3	X
#102four-state-96	398	0x00000100	0b1X	0
#103four-state-97	403	0x00000101	0b1X	1
#104four-state-98	408	0b0000000000000000000000010000000X	0b1X	X
#105four-state-99	411	0b0000000000000000000000010000000Z	0b1X	X
#106four-state-100	416	0x00000102	0b1X	1
#107four-state-101	420	0x00000103	0b1X	1
#108four-state-102	423	0b0000000000000000000000010000001X	0b1X	1
#109four-state-103	426	0b0000000000000000000000010000001Z	0b1X	1
#110four-state-104	431	0b000000000000000000000001000000X0	0b1X	X
#111four-state-105	436	0b000000000000000000000001000000X1	0b1X	1
#112four-state-106	441	0b000000000000000000000001000000XX	0b1X	X
#113four-state-107	444	0b000000000000000000000001000000XZ	0b1X	X
#114four-state-108	448	0b000000000000000000000001000000Z0	0b1X	X
#115four-state-109	453	0b000000000000000000000001000000Z1	0b1X	1
#116four-state-110	458	0b000000000000000000000001000000ZX	0b1X	X
#117four-state-111	461	0b000000000000000000000001000000ZZ	0b1X	X
#118four-state-112	466	0x00000100	0b1Z	0
#119four-state-113	471	0x00000101	0b1Z	1
#120four-state-114	476	0b0000000000000000000000010000000X	0b1Z	X
#121four-state-115	479	0b0000000000000000000000010000000Z	0b1Z	X
#122four-state-116	484	0x00000102	0b1Z	1
#123four-state-117	488	0x00000103	0b1Z	1
#124four-state-118	491	0b0000000000000000000000010000001X	0b1Z	1
#125four-state-119	494	0b0000000000000000000000010000001Z	0b1Z	1
#126four-state-120	499	0b000000000000000000000001000000X0	0b1Z	X
#127four-state-121	504	0b000000000000000000000001000000X1	0b1Z	1
#128four-state-122	509	0b000000000000000000000001000000XX	0b1Z	X
#129four-state-123	512	0b000000000000000000000001000000XZ	0b1Z	X
#130four-state-124	516	0b000000000000000000000001000000Z0	0b1Z	X
#131four-state-125	521	0b000000000000000000000001000000Z1	0b1Z	1
#132four-state-126	526	0b000000000000000000000001000000ZX	0b1Z	X
#133four-state-127	529	0b000000000000000000000001000000ZZ	0b1Z	X
#134four-state-128	534	0x00000100	0bX0	0
#135four-state-129	539	0x00000101	0bX0	X
#136four-state-130	543	0b0000000000000000000000010000000X	0bX0	X
#137four-state-131	546	0b0000000000000000000000010000000Z	0bX0	X
#138four-state-132	550	0x00000102	0bX0	X
#139four-state-133	553	0x00000103	0bX0	X
#140four-state-134	556	0b0000000000000000000000010000001X	0bX0	X
#141four-state-135	559	0b0000000000000000000000010000001Z	0bX0	X
#142four-state-136	563	0b000000000000000000000001000000X0	0bX0	X
#143four-state-137	567	0b000000000000000000000001000000X1	0bX0	X
#144four-state-138	571	0b000000000000000000000001000000XX	0bX0	X
#145four-state-139	574	0b000000000000000000000001000000XZ	0bX0	X
#146four-state-140	577	0b000000000000000000000001000000Z0	0bX0	X
#147four-state-141	581	0b000000000000000000000001000000Z1	0bX0	X
#148four-state-142	585	0b000000000000000000000001000000ZX	0bX0	X
#149four-state-143	588	0b000000000000000000000001000000ZZ	0bX0	X
#150four-state-144	593	0x00000100	0bX1	0
#151four-state-145	598	0x00000101	0bX1	1
#152four-state-146	602	0b0000000000000000000000010000000X	0bX1	X
#153four-state-147	605	0b0000000000000000000000010000000Z	0bX1	X
#154four-state-148	609	0x00000102	0bX1	X
#155four-state-149	613	0x00000103	0bX1	1
#156four-state-150	617	0b0000000000000000000000010000001X	0bX1	X
#157four-state-151	620	0b0000000000000000000000010000001Z	0bX1	X
#158four-state-152	624	0b000000000000000000000001000000X0	0bX1	X
#159four-state-153	628	0b000000000000000000000001000000X1	0bX1	1
#160four-state-154	632	0b000000000000000000000001000000XX	0bX1	X
#161four-state-155	635	0b000000000000000000000001000000XZ	0bX1	X
#162four-state-156	639	0b000000000000000000000001000000Z0	0bX1	X
#163four-state-157	643	0b000000000000000000000001000000Z1	0bX1	1
#164four-state-158	647	0b000000000000000000000001000000ZX	0bX1	X
#165four-state-159	650	0b000000000000000000000001000000ZZ	0bX1	X
#166four-state-160	655	0x00000100	0bXX	0
#167four-state-161	660	0x00000101	0bXX	X
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#172four-state-166	678	0b0000000000000000000000010000001X	0bXX	X
#173four-state-167	681	0b0000000000000000000000010000001Z	0bXX	X
#174four-state-168	685	0b000000000000000000000001000000X0	0bXX	X
#175four-state-169	689	0b000000000000000000000001000000X1	0bXX	X
#176four-state-170	693	0b000000000000000000000001000000XX	0bXX	X
#177four-state-171	696	0b000000000000000000000001000000XZ	0bXX	X
#178four-state-172	700	0b000000000000000000000001000000Z0	0bXX	X
#179four-state-173	704	0b000000000000000000000001000000Z1	0bXX	X
#180four-state-174	708	0b000000000000000000000001000000ZX	0bXX	X
#181four-state-175	711	0b000000000000000000000001000000ZZ	0bXX	X
#182four-state-176	716	0x00000100	0bXZ	0
#183four-state-177	721	0x00000101	0bXZ	X
#184four-state-178	725	0b0000000000000000000000010000000X	0bXZ	X
#185four-state-179	728	0b0000000000000000000000010000000Z	0bXZ	X
#186four-state-180	732	0x00000102	0bXZ	X
#187four-state-181	736	0x00000103	0bXZ	X
#188four-state-182	739	0b0000000000000000000000010000001X	0bXZ	X
#189four-state-183	742	0b0000000000000000000000010000001Z	0bXZ	X
#190four-state-184	746	0b000000000000000000000001000000X0	0bXZ	X
#191four-state-185	750	0b000000000000000000000001000000X1	0bXZ	X
#192four-state-186	754	0b000000000000000000000001000000XX	0bXZ	X
#193four-state-187	757	0b000000000000000000000001000000XZ	0bXZ	X
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#196four-state-190	769	0b000000000000000000000001000000ZX	0bXZ	X
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#198four-state-192	777	0x00000100	0bZ0	0
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#214four-state-208	836	0x00000100	0bZ1	0
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#248four-state-242	968	0b0000000000000000000000010000000X	0bZZ	X
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#254four-state-248	989	0b000000000000000000000001000000X0	0bZZ	X
#255four-state-249	993	0b000000000000000000000001000000X1	0bZZ	X
#256four-state-250	997	0b000000000000000000000001000000XX	0bZZ	X
#257four-state-251	1000	0b000000000000000000000001000000XZ	0bZZ	X
#258four-state-252	1004	0b000000000000000000000001000000Z0	0bZZ	X
#259four-state-253	1008	0b000000000000000000000001000000Z1	0bZZ	X
#260four-state-254	1012	0b000000000000000000000001000000ZX	0bZZ	X
#261four-state-255	1015	0b000000000000000000000001000000ZZ	0bZZ	X

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open alignment checker

Tests

RV32IMemoryAlignmentUnitTest includes six named binary cases and all \(4^4=256\) combinations of LOW/HIGH/X/Z for the four meaningful bits. It checks 262 checkpoints in each implementation. Source: src/modules/rv32i/RV32IMemoryAlignmentUnit.cpp (structural) and src/modules/rv32i/RV32IPipelineControlBehavioral.cpp (behavioral).

4.3.5.3. RV32IMemoryRequest

IO pins

Pin	Direction	Width	Description
CLK, RST	Input	1 each	Rising-edge transaction state; asynchronous active-high reset
ISSUE	Input	1	Capture a new request when idle
TAKE	Input	1	CPU can consume the current response
TAG	Input	32	Current CPU request identity; a change abandons the saved request
ADDR, WRITE_DATA	Input	32 each	Endpoint byte address and lane-placed data
OP	Input	3	Universal protocol operation (read=0, write=1); forwarded without decoding
WRITE_MASK	Input	4	Endpoint byte write enables
BUS_REQ_READY	Input	1	Endpoint can accept the request
BUS_RSP_VALID	Input	1	Endpoint holds a response
BUS_RSP_READ_DATA	Input	32	Endpoint response word
BUS_RSP_STATUS	Input	3	Universal response status; zero is success
BUS_REQ_VALID	Output	1	Saved request is awaiting acceptance
BUS_REQ_OP	Output	3	Saved operation
BUS_REQ_ADDR, BUS_REQ_WRITE_DATA	Output	32 each	Saved request payload
BUS_REQ_WRITE_MASK	Output	4	Saved byte mask
BUS_RSP_READY	Output	1	Consume or discard endpoint response
DONE	Output	1	A valid response belongs to the current CPU request
READ_DATA	Output	32	Direct copy of response data; meaningful with DONE
FAULT	Output	1	Nonzero response status; meaningful with DONE

Behavior

There is at most one outstanding transaction:

1. While idle, ISSUE and the live payload immediately drive the bus. If the transaction cannot finish on the first edge, capture tag/payload to hold it.
2. Keep BUS_REQ_VALID and the saved payload stable until a rising edge with BUS_REQ_READY=1. CPU input changes cannot mutate this request.
3. A response may arrive during the request cycle or after acceptance. DONE announces a matching valid response even if TAKE=0; the endpoint holds response data/status under this backpressure.
4. With TAKE or an abandoned tag, assert BUS_RSP_READY. A rising edge with response valid completes/drains the transaction. After completion, idle bypass exposes the next request during the following cycle. A ready zero-wait endpoint can therefore complete one request per cycle.

TAG is local bookkeeping, not a bus transaction ID. A mismatch immediately suppresses DONE and enables draining once the request has been sent. A mismatch sampled while busy is sticky: A→B→A across clock edges cannot make the old response valid again. A transient mismatch entirely between edges is not stored. Abandonment does not withdraw a stalled request or cancel an accepted store; it discards its eventual response. The CPU must choose tags that distinguish its requests and coordinate any redirects.

Reset clears busy/sent/abandoned and saved payload, suppresses bus valid/ready and DONE, and does not undo memory writes. Reset must be coordinated with the connected endpoint's transaction reset. READ_DATA and FAULT remain direct combinational response signals, even while idle or reset; they are not gated by DONE. ISSUE held high can start another transaction after the current one finishes, so the caller must manage it.

C++ example

This binary reference covers every output, payload hold, reset, completion, and abandonment rule. Start with reset asserted; input values must settle before each clock edge.

observe reads combinational outputs without advancing state. evaluate applies reset/edge changes and returns the resulting outputs. The core models use this distinction to capture all inputs from the old state.

namespace memory_access_example {
struct RequestInputs {
    bool CLK, RST, ISSUE, TAKE;
    uint32_t TAG, ADDR, WRITE_DATA;
    unsigned OP, WRITE_MASK;
    bool BUS_REQ_READY, BUS_RSP_VALID;
    uint32_t BUS_RSP_READ_DATA;
    unsigned BUS_RSP_STATUS;
};
struct RequestOutputs {
    bool DONE, FAULT;
    uint32_t READ_DATA;
    bool BUS_REQ_VALID, BUS_RSP_READY;
    unsigned BUS_REQ_OP;
    uint32_t BUS_REQ_ADDR, BUS_REQ_WRITE_DATA;
    unsigned BUS_REQ_WRITE_MASK;
};
class Request {
    bool busy=false, sent=false, abandoned=false, previous_clock=false;
    uint32_t tag=0, address=0, data=0;
    unsigned op=0, mask=0;
    bool discard(const RequestInputs& i) const { return busy && (abandoned || tag!=i.TAG); }
    RequestOutputs outputs(const RequestInputs& i) const {
        const bool sending=(busy||i.ISSUE)&&!sent&&!i.RST;
        const bool accepted=sending&&i.BUS_REQ_READY;
        return {(sent||accepted)&&i.BUS_RSP_VALID&&!discard(i)&&!i.RST,
                i.BUS_RSP_STATUS!=0,i.BUS_RSP_READ_DATA,
                sending,(sent||sending)&&(i.TAKE||discard(i))&&!i.RST,
                busy?op:i.OP,busy?address:i.ADDR,busy?data:i.WRITE_DATA,busy?mask:i.WRITE_MASK};
    }
public:
    RequestOutputs observe(const RequestInputs& i) const { return outputs(i); }
    RequestOutputs evaluate(const RequestInputs& i) {
        if (i.RST) {
            busy=sent=abandoned=false; tag=address=data=0; op=mask=0;
        } else if (!previous_clock && i.CLK) {
            const auto before=outputs(i);
            if (before.BUS_RSP_READY && i.BUS_RSP_VALID) busy=sent=abandoned=false;
            else if (!busy && i.ISSUE) {
                busy=true; sent=before.BUS_REQ_VALID&&i.BUS_REQ_READY; abandoned=false;
                tag=i.TAG; address=i.ADDR; data=i.WRITE_DATA; op=i.OP; mask=i.WRITE_MASK;
            } else if (busy) {
                abandoned=discard(i);
                if (before.BUS_REQ_VALID && i.BUS_REQ_READY) sent=true;
            }
        }
        previous_clock=i.CLK;
        return outputs(i);
    }
};
}

Unknown inputs and timing

State is initially unknown until reset. Four-state behavior follows the FF cells, payload registers, equality gates, and enables. Response data is rewired and preserves X/Z; status is OR-reduced. The example assumes binary, stable handshake controls and does not model setup/hold violations or propagation glitches. Request/response handshakes are sampled on clock edges, not whenever valid and ready happen to overlap between edges.

Implementation

Structural implementation

BUSY, SENT, and ABANDONED are always-clocked ClockedStateBit children. The general requester retains five fields in Register children. Payload multiplexers select live fields while idle and held fields while busy. TAG_MATCH is a fixed structural RV32IRequestTagMatch: inputs CURRENT[32] and SAVED[32] feed 32 XOR comparisons and an OR-reduction tree, producing CHANGED. Payload, handshake state, and response handling remain visible at the requester level.

Payload register	Width	Purpose
REQUEST_TAG	32	Compare the saved request identity with the current tag
REQUEST_OP	3	Hold the operation while the request is pending
REQUEST_ADDR	32	Hold the byte address
REQUEST_WRITE_DATA	32	Hold the store data
REQUEST_WRITE_MASK	4	Hold the byte enables

These are 103 payload bits plus three handshake-state bits. A payload register is one word with shared CLK/RST/WE, not independently addressed bits. Its structural implementation contains FF cells; its behavioral implementation stores the same vector in one component.

The advanced core's fetch requester is read-only and uses its saved address as the request tag. It stores only REQUEST_ADDR (32 payload bits), while driving the constant Read operation, zero write data, and full byte mask onto the bus. The general data requester retains all five fields, including its variable store payload, to keep a pending request stable under backpressure.

Response data is wired straight from BUS_RSP_READ_DATA to READ_DATA; there is no response register. The retained request/state is why a requester cannot be replaced with a port rename.

Behavioral implementation

RV32IMemoryRequestBehavioral holds its own four-state BUSY, SENT, and ABANDONED bits and saved request fields. It evaluates the request, response, tag-comparison, and register rules used by the structural requester, including uncertain inputs. The compact cores use the separate binary MemoryRequestState for their instruction and data requests. Catalog-selected outputs follow the requester’s characterized combinational or clock-to-output delays. Fault is still the OR of the status bits and response data is passed through unchanged.

Request presence, reset qualification and response validity are prepared before the late TAKE/discard decision. This shortens the combinational completion path without adding a cycle or changing when either handshake is accepted.

Examples

All 21 recorded rows of RV32IMemoryRequestTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (2d30c34a9a12ed13). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	ADDRInput · 32 bit	BUS_REQ_READYInput · 1 bit	BUS_RSP_READ_DATAInput · 32 bit	BUS_RSP_STATUSInput · 3 bit	BUS_RSP_VALIDInput · 1 bit	CLKInput · 1 bit	ISSUEInput · 1 bit	OPInput · 3 bit	RSTInput · 1 bit	TAGInput · 32 bit	TAKEInput · 1 bit	WRITE_DATAInput · 32 bit	WRITE_MASKInput · 4 bit	BUS_REQ_ADDRExpected output · 32 bit	BUS_REQ_OPExpected output · 3 bit	BUS_REQ_VALIDExpected output · 1 bit	BUS_REQ_WRITE_DATAExpected output · 32 bit	BUS_REQ_WRITE_MASKExpected output · 4 bit	BUS_RSP_READYExpected output · 1 bit	DONEExpected output · 1 bit	FAULTExpected output · 1 bit	READ_DATAExpected output · 32 bit
#0reset	13	0x00000100	0	0x00000000	0x0	0	0	0	0x1	1	0x00000000	0	0x12345678	0xF	0x00000100	not checked	0	not checked	not checked	0	0	not checked	not checked
#1issue-before-edge	23	0x00000100	0	0x00000000	0x0	0	0	1	0x1	0	0x00000000	0	0x12345678	0xF	0x00000100	not checked	1	not checked	not checked	0	0	not checked	not checked
#2capture	35	0x00000100	0	0x00000000	0x0	0	1	1	0x1	0	0x00000000	0	0x12345678	0xF	0x00000100	not checked	1	not checked	not checked	0	0	not checked	not checked
#3payload-held	40	0x00000200	0	0x00000000	0x0	0	0	0	0x0	0	0x00000000	0	0x00000000	0x0	0x00000100	0x1	1	0x12345678	0xF	not checked	not checked	not checked	not checked
#4backpressure-edge	45	0x00000200	0	0x00000000	0x0	0	1	0	0x0	0	0x00000000	0	0x00000000	0x0	0x00000100	not checked	1	not checked	not checked	0	0	not checked	not checked
#5accept-setup	54	0x00000200	1	0x00000000	0x0	0	0	0	0x0	0	0x00000000	0	0x00000000	0x0	0x00000100	not checked	1	not checked	not checked	0	0	not checked	not checked
#6accepted	63	0x00000200	1	0x00000000	0x0	0	1	0	0x0	0	0x00000000	0	0x00000000	0x0	0x00000100	not checked	0	not checked	not checked	0	0	not checked	not checked
#7response-held	68	0x00000200	1	0x89ABCDEF	0x2	1	0	0	0x0	0	0x00000000	0	0x00000000	0x0	not checked	not checked	not checked	not checked	not checked	0	1	1	0x89ABCDEF
#8response-held-edge	73	0x00000200	1	0x89ABCDEF	0x2	1	1	0	0x0	0	0x00000000	0	0x00000000	0x0	0x00000100	not checked	0	not checked	not checked	0	1	not checked	not checked
#9take-setup	85	0x00000200	1	0x89ABCDEF	0x2	1	0	0	0x0	0	0x00000000	1	0x00000000	0x0	0x00000100	not checked	0	not checked	not checked	1	1	not checked	not checked
#10taken	96	0x00000200	1	0x89ABCDEF	0x2	1	1	0	0x0	0	0x00000000	1	0x00000000	0x0	0x00000200	not checked	0	not checked	not checked	0	0	not checked	not checked
#11new-issue-setup	109	0x00000200	0	0x89ABCDEF	0x2	0	0	1	0x0	0	0x00000004	0	0x00000000	0x0	0x00000200	not checked	1	not checked	not checked	0	0	not checked	not checked
#12second-capture	126	0x00000200	0	0x89ABCDEF	0x2	0	1	1	0x0	0	0x00000004	0	0x00000000	0x0	0x00000200	not checked	1	not checked	not checked	0	0	not checked	not checked
#13redirect-before-accept	143	0x00000200	0	0x89ABCDEF	0x2	0	0	0	0x0	0	0x00000008	0	0x00000000	0x0	0x00000200	not checked	1	not checked	not checked	1	0	not checked	not checked
#14record-abandonment	149	0x00000200	0	0x89ABCDEF	0x2	0	1	0	0x0	0	0x00000008	0	0x00000000	0x0	0x00000200	not checked	1	not checked	not checked	1	0	not checked	not checked
#15tag-returns-ABA	158	0x00000200	1	0x89ABCDEF	0x2	0	0	0	0x0	0	0x00000004	0	0x00000000	0x0	0x00000200	not checked	1	not checked	not checked	1	0	not checked	not checked
#16abandoned-accepted	167	0x00000200	1	0x89ABCDEF	0x2	0	1	0	0x0	0	0x00000004	0	0x00000000	0x0	0x00000200	not checked	0	not checked	not checked	1	0	not checked	not checked
#17stale-response	179	0x00000200	1	0x89ABCDEF	0x2	1	0	0	0x0	0	0x00000004	0	0x00000000	0x0	0x00000200	not checked	0	not checked	not checked	1	0	not checked	not checked
#18stale-drained	189	0x00000200	1	0x89ABCDEF	0x2	1	1	0	0x0	0	0x00000004	0	0x00000000	0x0	0x00000200	not checked	0	not checked	not checked	0	0	not checked	not checked
#19ungated-response-wires	194	0x00000200	1	0x89ABCDEF	0x2	0	0	0	0x0	0	0x00000004	0	0x00000000	0x0	not checked	not checked	not checked	not checked	not checked	not checked	0	1	0x89ABCDEF
#20reset-again	208	0x00000200	1	0x89ABCDEF	0x2	0	0	0	0x0	1	0x00000004	0	0x00000000	0x0	0x00000200	not checked	0	not checked	not checked	0	0	not checked	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open memory requester

Tests

RV32IMemoryRequestTest records 21 checkpoints: capture, backpressure, payload stability, acceptance, held response, faults, redirect/ABA abandonment, draining, and reset. RV32IMemoryMigrationTest checks transaction endpoints and zero-wait single-cycle integration. RV32IBuildingBlocksDocumentationTest executes the C++ examples. Sources: RV32IMemoryLanes.cpp and RV32IMemoryRequest.cpp.