§ 4.5.2. Fetch

RV32IBaselineFetchStage owns the fetch PC and exposes native instruction-memory pins. The fetch PC is ahead of the architectural PC reported by Writeback while instructions are in flight.

Component	Description	Structural	Behavioral
RV32IBaselineFetchStage	Fetch PC, PC+4/redirect selection, instruction and fault packet	Yes	Yes

IO pins

Pin	Direction	Width	Description
CLK, RST	Input	1 each	Rising-edge capture; asynchronous active-high reset
PC_WRITE, PC_REDIRECT	Input	1 each	PC update permission; select REDIRECT_PC rather than PC+4
FETCH_VALID	Input	1	Instruction read enable and outgoing packet validity
REDIRECT_PC	Input	32	Resolved branch/jump target or fallthrough
IMEM_READ_DATA, IMEM_FAULT	Input	32, 1	Direct instruction word and access fault
IMEM_WORD_ADDR, IMEM_READ_EN	Output	32, 1	Word index PC/4 and read enable
FETCH_PC	Output	32	Current fetch PC, in bytes
OUT_VALID	Output	1	Follows FETCH_VALID
OUT_PC, OUT_INSTRUCTION, OUT_FETCH_STATUS	Output	32 each	IF/ID packet fields

Behavior

Reset sets PC to zero. With PC_WRITE=1, a known rising edge selects REDIRECT_PC when PC_REDIRECT=1, otherwise PC+4. Without that edge and enable, PC holds. FETCH_VALID controls read enable independently of PC_WRITE: redirecting a PC does not have to accept an instruction on the same edge.

OUT_PC is the current PC; OUT_INSTRUCTION directly follows IMEM_READ_DATA. FETCH_STATUS bit 0 reports nonzero PC bits 1:0, and bit 1 follows IMEM_FAULT. A fault is recorded in the packet, not acted on immediately. Invalid or unaccepted packets cannot trap.

C++ example

The examples use the shared Packet definition. Fetch writes only the three IF/ID fields and validity. This model contains no instruction storage or pending request.

struct Fetch {
    uint32_t pc=0;
    bool previous_clock=false;
    struct Outputs { Packet packet; uint32_t fetch_pc, word_addr; bool read_en; };
    Outputs evaluate(bool clk, bool reset, bool pc_write, bool redirect,
                     uint32_t redirect_pc, bool fetch_valid,
                     uint32_t instruction, bool fault) {
        if(reset) pc=0;
        else if(!previous_clock && clk && pc_write) pc=redirect?redirect_pc:pc+4;
        previous_clock=clk;
        Packet p;
        p.valid=fetch_valid; p.pc=pc; p.instruction=instruction;
        p.fetch_status=uint32_t(bool(pc&3)) | (uint32_t(fault)<<1);
        return {p,pc,pc>>2,fetch_valid};
    }
};

Implementation

Structural implementation

FETCH_DATAPATH reuses RV32ISingleCycleFetchStage: Register<32>, the structural PC+4 incrementer, alignment check, and direct memory-port rewiring. NEXT_PC_SELECT chooses PC+4 or the resolved redirect. FETCH_STATUS_PACK groups the two fault bits.

Behavioral implementation

The Fetch branch of BehavioralStage stores a four-state PC and previous clock, then produces the same native pins and IF/ID packet. It applies the register, incrementer, and redirect mux's four-state rules, so an uninitialized or uncertain PC is not converted to zero. Its contract is rv32i.baseline.fetch. The documented cross-fidelity checks cover settled binary operation after reset; they do not establish equivalence for every uninitialized or X-valued PC.

Examples

The rows cover reset, direct read, sequential advance, hold, redirect, alignment, and access faults. Times and checkpoint numbers come from the runnable scenario.

All 10 recorded rows of RV32IBaselineFetchStageTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: baseline-structural-stages / structural (f72af366c5dca6eb). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	CLKInput · 1 bit	FETCH_VALIDInput · 1 bit	IMEM_FAULTInput · 1 bit	IMEM_READ_DATAInput · 32 bit	PC_REDIRECTInput · 1 bit	PC_WRITEInput · 1 bit	REDIRECT_PCInput · 32 bit	RSTInput · 1 bit	FETCH_PCExpected output · 32 bit	IMEM_READ_ENExpected output · 1 bit	IMEM_WORD_ADDRExpected output · 32 bit	OUT_FETCH_STATUSExpected output · 32 bit	OUT_INSTRUCTIONExpected output · 32 bit	OUT_PCExpected output · 32 bit	OUT_VALIDExpected output · 1 bit
#0initial-inputs	13	0	0	0	0x00000000	0	0	0x00000000	1	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#1reset	14	0	0	0	0x00000000	0	0	0x00000000	1	0x00000000	not checked	not checked	not checked	not checked	not checked	0
#2read-before-edge	15	0	1	0	0x00500093	0	1	0x00000000	0	not checked	not checked	0x00000000	not checked	0x00500093	0x00000000	1
#3advance	25	1	1	0	0x00500093	0	1	0x00000000	0	0x00000004	not checked	0x00000001	not checked	not checked	not checked	not checked
#4hold-setup	26	0	0	0	0x00500093	0	0	0x00000000	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#5hold	31	1	0	0	0x00500093	0	0	0x00000000	0	0x00000004	not checked	not checked	not checked	not checked	not checked	0
#6redirect-setup	35	0	0	0	0x00500093	1	1	0x00000102	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#7redirect-with-alignment-status	44	1	0	0	0x00500093	1	1	0x00000102	0	0x00000102	not checked	0x00000040	0x00000001	not checked	not checked	not checked
#8fetch-fault	45	1	0	1	0x00500093	1	1	0x00000102	0	not checked	not checked	not checked	0x00000003	not checked	not checked	not checked
#9reset-again	54	1	0	0	0x00500093	1	1	0x00000102	1	0x00000000	not checked	not checked	0x00000000	not checked	not checked	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Open Fetch stage

Tests

RV32IBaselineFetchStageTest compares both implementations. The core test checks that a branch redirect does not accept the old instruction-memory word. Sources: RV32IBaselinePipeline.cpp, RV32IBaselinePipelineBehavioral.cpp.