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§ 4.6. Advanced Pipeline

RV32IFiveStageCore keeps the five stages and four packet registers from the baseline. It changes how operands arrive, how Fetch chooses its next address, and when the pipeline advances. It is still a single-issue, in-order RV32I core—not a new instruction set or an out-of-order processor.

Component Description Structural Behavioral
RV32IFetchStage Fetch PC and IF/ID packet; advanced core uses prediction's external next PC Yes Yes
RV32IMemoryStage Memory access and MEM/WB packet with request and forwarding signals Yes Yes
RV32IForwardingUnit Select the newest available operand Yes Yes
RV32IHazardDetectionUnit Detect the remaining immediate load dependency Yes Yes
RV32IPredictionCounter One-bit / saturating two-bit state transition Yes Yes
RV32IBranchPredecode Extract fetch-time conditional and direct-jump targets Yes Yes
RV32IBranchPredictor Switchable direction policy and indexed state Yes Yes
RV32IBranchRecovery Compare saved and actual next PC; qualify updates Yes Yes
RV32IPredictionPath Group prediction, packet metadata, and recovery Yes Yes
RV32IPipelineCoordinator Combine waits, hazards, corrections, and terminal priority Yes Yes
RV32IFiveStageCore Complete advanced pipeline with universal memory ports Yes Yes

Changes from the baseline

Boundary Retained Added or changed
Fetch PC state and instruction acceptance Predict next PC; retain one outstanding request when memory waits
Decode Decoder, register file, packed controls WB-to-ID bypass; stall only the immediate load-use dependency
Execute Shared RV32ISingleCycleExecuteStage and Next-PC datapath EX/MEM and MEM/WB operand forwarding; expose actual branch direction
Memory Alignment, load/store lanes, in-order effects Transaction completion can hold the pipeline
Writeback Combinational RV32IWritebackStage, separate execution status No new WB register or retirement-history circuit
Pipeline registers IF/ID, ID/EX, EX/MEM, MEM/WB contracts Two parallel 32-bit next-PC metadata registers; same enables, no additional stage

The ALU, register file, instruction decoding, packet encoding, and architectural retirement rules remain those documented in §§4.2–4.5. Forwarding describes the changed Decode/Execute interfaces; memory waits describes Fetch/Memory coordination.

Prediction travels with the instruction Fetch predecodes a target and predicts a next PC. The prediction is captured in IF/ID then ID/EX alongside its instruction. Recovery compares both Execute candidate addresses in parallel, then selects the mismatch using the branch or jump decision. FETCH · CURRENT INSTRUCTION Predecode PC + B/J immediate Predictor choose next PC IF/ID metadata capture prediction Used immediately as Fetch's next address. A copy follows the accepted instruction. edge EXECUTE · THAT SAME INSTRUCTION Execute candidates + taken Recovery parallel compares ID/EX metadata saved prediction Coordinator advance · hold · flush On an accepted resolution: correct if needed; train conditional branches once.
Two metadata registers, not two extra stages. They use the real IF/ID and ID/EX write enables. Recovery asks the coordinator to correct Fetch and discard younger work; a memory wait delays that action and training together.

Section map

Section Main contract
4.6.1. Operand Forwarding Producer priority, WB bypass, grouped Execute
4.6.2. Load-Use Hazards Hold the consumer, insert a bubble, advance the producer
4.6.3. Branch Prediction Predecode, five policies, FF counter table
4.6.4. Prediction Recovery Saved prediction, correction, flush and training priority
4.6.5. Memory Wait Handling Zero-wait and delayed endpoints; movement coordinator
4.6.6. Complete Advanced Core Assembly, configuration, observations and program checks

Each unblocked instruction advances one stage at each rising edge. After filling, an independent instruction stream can retire one instruction per cycle. A single instruction still crosses five stages. Hazards, prediction misses, and memory waits reduce throughput.

Both fidelities implement the same settled binary signals and clock-edge behavior after reset. Catalog-selected behavioral components carry gate-derived delay tables; smaller eligible parts can use a delay twin for the current values, while the complete core and self-timed memory parts use their tables. Propagation delays can vary within a run, while the selected CPU clock period is fixed. Neither is a measured hardware frequency. Caches, BTBs, return-address stacks, speculative memory writes, and multiple outstanding requests are outside this section.