Program 15: Misaligned jump target

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Purpose

Reject JALR's target alignment on the jump instruction itself.

This is a negative test: the named trap is the expected outcome, not a failed simulation.

Setup

Property	Value
Benchmark workload ID	program-15
Headless selection	--program 15
Visualizer scenario	rv32i-program15
Registered test	RV32ISingleCycleSystemTest/program-15
Instruction image	2 words, starting at 0x00000000; last word at 0x00000004
Initial state	PC = 0x00000000; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
x1	Candidate target address 2

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

addi x1, x0, 2                 # 0x00000000 | 0x00200093
jalr x0, 0(x1)                 # 0x00000004 | 0x00008067

Execution

1. ADDI sets the candidate target to byte address 2.
2. JALR at 0x04 adds zero and clears target bit 0. Address 2 is still 2 because bit 1, not bit 0, is set.
3. The target violates four-byte instruction alignment. InstructionAddressMisaligned is recorded on JALR, PC remains 0x04, and no fetch at address 2 occurs.

The destination is x0, so this fixture does not test preservation of a nonzero link register. The separate instruction boundary examples cover that case.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
x1	0x00000002	Candidate target address 2
PC	0x00000004	Faulting attempt address
Attempts	2	Checkpoints I0–I1
HALTED	0	No EBREAK halt
TRAPPED	1	Expected terminal exception
TRAP_CAUSE	3	InstructionAddressMisaligned, a project enum code

Start address	Bytes, in increasing address order
None	—

No data writes occur; the initial data image is unchanged. Two attempts occur. Compare Program 16: an aligned inaccessible target is accepted before its next fetch faults.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 15 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 2 instruction attempts are included, with absolute simulator time and checkpoint number. The terminal fault is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 2 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-15, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7080	ADDI @ 0x00000000	raw=0x00200093, pc_after=0x00000004, wb=x1=0x00000002, mem=None, flow=next
I1	11080	JALR @ 0x00000004	raw=0x00008067, pc_after=0x00000004, wb=None, mem=None, jump=JALR, trapped=true cause=InstructionAddressMisaligned

Open program 15 reference