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Program 4: Conditional branches and fallthrough

Program catalogue · Instruction reference · Executable reference

Purpose

Exercise all six RV32I conditional branch forms, including signed/unsigned interpretation and a not-taken branch.

This is an instruction-behavior correctness fixture.

Setup

Property Value
Benchmark workload ID program-04
Headless selection --program 4
Visualizer scenario rv32i-program4
Registered test RV32ISingleCycleSystemTest/program-04
Instruction image 31 words, starting at 0x00000000; last word at 0x00000078
Initial state PC = 0x00000000; all registers zero; neither halted nor trapped
Memories Separate instruction and data memories, 256 KiB each; unlisted data bytes zero
Start address Bytes, in increasing address order
None —

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register Role established by the program
x1, x2 Equality operands, initially 5 and 5; x2 later becomes 6
x3 Bit pattern for -1
x4 Comparison operand 1
x10 Score
x11 Output address 0x120

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

addi x10, x0, 0                # 0x00000000 | 0x00000513
addi x1, x0, 5                 # 0x00000004 | 0x00500093
addi x2, x0, 5                 # 0x00000008 | 0x00500113
beq x1, x2, L_14               # 0x0000000C | 0x00208463
addi x10, x10, 100             # 0x00000010 | 0x06450513
L_14:
addi x10, x10, 1               # 0x00000014 | 0x00150513
addi x2, x0, 6                 # 0x00000018 | 0x00600113
bne x1, x2, L_24               # 0x0000001C | 0x00209463
addi x10, x10, 100             # 0x00000020 | 0x06450513
L_24:
addi x10, x10, 1               # 0x00000024 | 0x00150513
addi x3, x0, -1                # 0x00000028 | 0xFFF00193
addi x4, x0, 1                 # 0x0000002C | 0x00100213
blt x3, x4, L_38               # 0x00000030 | 0x0041C463
addi x10, x10, 100             # 0x00000034 | 0x06450513
L_38:
addi x10, x10, 1               # 0x00000038 | 0x00150513
bge x4, x3, L_44               # 0x0000003C | 0x00325463
addi x10, x10, 100             # 0x00000040 | 0x06450513
L_44:
addi x10, x10, 1               # 0x00000044 | 0x00150513
bltu x4, x3, L_50              # 0x00000048 | 0x00326463
addi x10, x10, 100             # 0x0000004C | 0x06450513
L_50:
addi x10, x10, 1               # 0x00000050 | 0x00150513
bgeu x3, x4, L_5C              # 0x00000054 | 0x0041F463
addi x10, x10, 100             # 0x00000058 | 0x06450513
L_5C:
addi x10, x10, 1               # 0x0000005C | 0x00150513
beq x1, x4, L_6C               # 0x00000060 | 0x00408663
addi x10, x10, 1               # 0x00000064 | 0x00150513
jal x0, L_70                   # 0x00000068 | 0x0080006F
L_6C:
addi x10, x10, 100             # 0x0000006C | 0x06450513
L_70:
addi x11, x0, 0x120            # 0x00000070 | 0x12000593
sw x10, 0(x11)                 # 0x00000074 | 0x00A5A023
ebreak                         # 0x00000078 | 0x00100073

Execution

  1. Start the score at zero. BEQ for 5 == 5 and BNE for 5 != 6 each take a branch over an incorrect-path +100 instruction, then add one.
  2. BLT tests signed -1 < 1; BGE tests signed 1 >= -1. Both take their branches and add one.
  3. BLTU tests unsigned 1 < 0xFFFFFFFF; BGEU tests unsigned 0xFFFFFFFF >= 1. Both take their branches and add one.
  4. The final BEQ compares 5 with 1 and must not branch. Its fallthrough adds the seventh point. JAL then skips the incorrect-path +100 before storing the score.
  5. Store 7 at 0x120 and halt. Seven wrong-path additions are skipped: 31 loaded words produce 24 attempts.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item Expected value Meaning
x10 0x00000007 Score
x11 0x00000120 Output address 0x120
PC 0x00000078 EBREAK address
Attempts 24 Checkpoints I0–I23
HALTED 1 Project halt
TRAPPED 0 No exception
TRAP_CAUSE 0 None, a project enum code
Start address Bytes, in increasing address order
0x00000120 07 00 00 00

All data bytes not listed as written retain their initial values. A score other than 7 exposes a comparison, branch-target, or fallthrough error. The six initial taken branches and the final not-taken BEQ are distinct cases.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 4 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 24 instruction attempts are included, with absolute simulator time and checkpoint number. The terminating EBREAK is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 24 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-04, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

CheckpointTimeInstruction / addressExpected architectural effects
I07080ADDI @ 0x00000000raw=0x00000513, pc_after=0x00000004, wb=x10=0x00000000, mem=None, flow=next
I111080ADDI @ 0x00000004raw=0x00500093, pc_after=0x00000008, wb=x1=0x00000005, mem=None, flow=next
I215080ADDI @ 0x00000008raw=0x00500113, pc_after=0x0000000c, wb=x2=0x00000005, mem=None, flow=next
I319080BEQ @ 0x0000000craw=0x00208463, pc_after=0x00000014, wb=None, mem=None, branch=BEQ taken=true
I423080ADDI @ 0x00000014raw=0x00150513, pc_after=0x00000018, wb=x10=0x00000001, mem=None, flow=next
I527080ADDI @ 0x00000018raw=0x00600113, pc_after=0x0000001c, wb=x2=0x00000006, mem=None, flow=next
I631080BNE @ 0x0000001craw=0x00209463, pc_after=0x00000024, wb=None, mem=None, branch=BNE taken=true
I735080ADDI @ 0x00000024raw=0x00150513, pc_after=0x00000028, wb=x10=0x00000002, mem=None, flow=next
I839080ADDI @ 0x00000028raw=0xfff00193, pc_after=0x0000002c, wb=x3=0xffffffff, mem=None, flow=next
I943080ADDI @ 0x0000002craw=0x00100213, pc_after=0x00000030, wb=x4=0x00000001, mem=None, flow=next
I1047080BLT @ 0x00000030raw=0x0041c463, pc_after=0x00000038, wb=None, mem=None, branch=BLT taken=true
I1151080ADDI @ 0x00000038raw=0x00150513, pc_after=0x0000003c, wb=x10=0x00000003, mem=None, flow=next
I1255080BGE @ 0x0000003craw=0x00325463, pc_after=0x00000044, wb=None, mem=None, branch=BGE taken=true
I1359080ADDI @ 0x00000044raw=0x00150513, pc_after=0x00000048, wb=x10=0x00000004, mem=None, flow=next
I1463080BLTU @ 0x00000048raw=0x00326463, pc_after=0x00000050, wb=None, mem=None, branch=BLTU taken=true
I1567080ADDI @ 0x00000050raw=0x00150513, pc_after=0x00000054, wb=x10=0x00000005, mem=None, flow=next
I1671080BGEU @ 0x00000054raw=0x0041f463, pc_after=0x0000005c, wb=None, mem=None, branch=BGEU taken=true
I1775080ADDI @ 0x0000005craw=0x00150513, pc_after=0x00000060, wb=x10=0x00000006, mem=None, flow=next
I1879080BEQ @ 0x00000060raw=0x00408663, pc_after=0x00000064, wb=None, mem=None, branch=BEQ taken=false
I1983080ADDI @ 0x00000064raw=0x00150513, pc_after=0x00000068, wb=x10=0x00000007, mem=None, flow=next
I2087080JAL @ 0x00000068raw=0x0080006f, pc_after=0x00000070, wb=x0=0x0000006c ignored-x0, mem=None, jump=JAL
I2191080ADDI @ 0x00000070raw=0x12000593, pc_after=0x00000074, wb=x11=0x00000120, mem=None, flow=next
I2295080SW @ 0x00000074raw=0x00a5a023, pc_after=0x00000078, wb=None, mem=Write Word @0x00000120 <- 0x00000007, flow=next
I2399080EBREAK @ 0x00000078raw=0x00100073, pc_after=0x00000078, wb=None, mem=None, flow=next, halted=true

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