Program 6: Upper immediates, PC-relative values, and FENCE¶

Program catalogue · Instruction reference · Executable reference

Purpose¶

Construct a full-width constant, read PC-relative values with AUIPC, and execute a no-effect FENCE.

This is an instruction-behavior correctness fixture.

Setup¶

Property	Value
Benchmark workload ID	`program-06`
Headless selection	`--program 6`
Visualizer scenario	`rv32i-program6`
Registered test	`RV32ISingleCycleSystemTest/program-06`
Instruction image	10 words, starting at `0x00000000`; last word at `0x00000024`
Initial state	PC = `0x00000000`; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
`x1`	Constructed constant 0x12345678
`x2`	PC of AUIPC at 0x08
`x3`	PC of AUIPC at 0x0C plus 0x1000
`x4`	Output base at 0x120

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly¶

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

lui x1, 0x12345                # 0x00000000 | 0x123450B7
addi x1, x1, 0x678             # 0x00000004 | 0x67808093
auipc x2, 0x00000              # 0x00000008 | 0x00000117
auipc x3, 0x00001              # 0x0000000C | 0x00001197
fence 0, 0                     # 0x00000010 | 0x0000000F
addi x4, x0, 0x120             # 0x00000014 | 0x12000213
sw x1, 0(x4)                   # 0x00000018 | 0x00122023
sw x2, 4(x4)                   # 0x0000001C | 0x00222223
sw x3, 8(x4)                   # 0x00000020 | 0x00322423
ebreak                         # 0x00000024 | 0x00100073

Execution¶

LUI places 0x12345 in the upper twenty bits. ADDI supplies the low 0x678, forming 0x12345678.
AUIPC at 0x08 with upper immediate zero writes 0x08 to x2. AUIPC at 0x0C with upper immediate one writes 0x100C to x3. Each uses its own instruction address, not PC+4.
The fixture's exact fence word is 0x0000000F, shown as fence 0, 0: both predecessor and successor sets are empty. It changes no register or memory data in this serial reference.
Store the three results at 0x120, 0x124, and 0x128, then halt after ten attempts.

Expected result¶

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
`x1`	`0x12345678`	Constructed constant 0x12345678
`x2`	`0x00000008`	PC of AUIPC at 0x08
`x3`	`0x0000100C`	PC of AUIPC at 0x0C plus 0x1000
`PC`	`0x00000024`	EBREAK address
`Attempts`	10	Checkpoints I0–I9
`HALTED`	1	Project halt
`TRAPPED`	0	No exception
`TRAP_CAUSE`	0	`None`, a project enum code

Start address	Bytes, in increasing address order
`0x00000120`	`78 56 34 12`
`0x00000124`	`08 00 00 00`
`0x00000128`	`0C 10 00 00`

All data bytes not listed as written retain their initial values. The FENCE case is not a cache flush or a proof of multicore ordering. The assembly lists unshifted U-format operands; the resulting register values are shifted by twelve bits.

Simulation and checkpoints¶

For a headless functional check, run build/rv32i_experiment --core single --program 6 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 10 instruction attempts are included, with absolute simulator time and checkpoint number. The terminating EBREAK is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 10 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-06, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7092	`LUI @ 0x00000000`	`raw=0x123450b7, pc_after=0x00000004, wb=x1=0x12345000, mem=None, flow=next`
I1	11092	`ADDI @ 0x00000004`	`raw=0x67808093, pc_after=0x00000008, wb=x1=0x12345678, mem=None, flow=next`
I2	15092	`AUIPC @ 0x00000008`	`raw=0x00000117, pc_after=0x0000000c, wb=x2=0x00000008, mem=None, flow=next`
I3	19092	`AUIPC @ 0x0000000c`	`raw=0x00001197, pc_after=0x00000010, wb=x3=0x0000100c, mem=None, flow=next`
I4	23092	`FENCE @ 0x00000010`	`raw=0x0000000f, pc_after=0x00000014, wb=None, mem=None, flow=next`
I5	27092	`ADDI @ 0x00000014`	`raw=0x12000213, pc_after=0x00000018, wb=x4=0x00000120, mem=None, flow=next`
I6	31092	`SW @ 0x00000018`	`raw=0x00122023, pc_after=0x0000001c, wb=None, mem=Write Word @0x00000120 <- 0x12345678, flow=next`
I7	35092	`SW @ 0x0000001c`	`raw=0x00222223, pc_after=0x00000020, wb=None, mem=Write Word @0x00000124 <- 0x00000008, flow=next`
I8	39092	`SW @ 0x00000020`	`raw=0x00322423, pc_after=0x00000024, wb=None, mem=Write Word @0x00000128 <- 0x0000100c, flow=next`
I9	43092	`EBREAK @ 0x00000024`	`raw=0x00100073, pc_after=0x00000024, wb=None, mem=None, flow=next, halted=true`

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