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§ 4.4. Single-Cycle Core

RV32ISingleCycleCore connects six logical datapath stages and a shared execution-status unit. Each stage has structural and behavioral implementations under the same pin contract. 4.1 specifies the instructions; 4.2 specifies the reused building blocks.

Each enabled instruction completes at one rising edge after the full combinational path settles. Instruction and data memories read asynchronously; stores, PC, and register writes commit together. There are no request buffers, IF/ID/EX/MEM/WB pipeline registers, or overlapped instructions. Variable-latency endpoints are supported by the advanced RV32IFiveStageCore, not this strict single-cycle core or the baseline pipeline. See the memory compatibility table.

Components

Component Description Structural Behavioral
RV32ISingleCycleFetchStage PC storage, PC+4, direct instruction read, fetch status Yes Yes
RV32ISingleCycleDecodeStage Instruction decoding and the architectural register file Yes Yes
RV32ISingleCycleExecuteStage Shared ALU, operand selection, branch comparison, jump/branch targets Yes Yes
RV32ISingleCycleMemoryStage Direct data access, commit-gated stores, and lane formatting Yes Yes
RV32ISingleCycleWritebackStage Select the value to write to a destination register Yes Yes
RV32ISingleCycleNextPCStage Select the next PC and check an active transfer's alignment Yes Yes
RV32ISingleCycleCore Connect the six stages, execution status, and two external memory ports Yes Yes

Columns describe registered simulator implementations, not the simplified C++ examples. RV32IExecutionControlStatusUnit is reused from 4.3.6, with both implementations; it is not a seventh datapath stage.

Contents

Section Coverage
4.4.1. Fetch PC, PC+4, direct instruction read, reset
4.4.2. Decode and Register Read Decoding controls, two reads, one completion-edge write, x0
4.4.3. Execute Operand selectors, one shared ALU, branch conditions, target generation
4.4.4. Memory Access Direct pins, byte lanes, sign extension, faults, store permission
4.4.5. Writeback Zero/ALU/load/link selection; no storage
4.4.6. Next PC Fallthrough versus transfer, target alignment; no PC storage
4.4.7. Complete Core Full wiring, completion, compatible memory endpoints, instruction examples and tests

Each stage page follows IO pins → behavior and C++ example → structural/behavioral implementation → examples and embedded simulation → tests. Its scrollable example table contains all recorded rows, including checkpoint numbers and simulator times. The C++ examples reuse explicitly linked 4.3 models rather than redefining the decoder, ALU, or lane operations.

Datapath and state ownership

Stage roles

Five roles in logical order Fetch obtains the instruction, Decode reads registers, Execute computes, Memory accesses data if needed, and Writeback selects the destination value, without inter-stage pipeline registers. FETCH Instruction and PC DECODE Decode and register read EXECUTE ALU and targets MEMORY Data access if required WRITEBACK Destination value
Logical order, not five clock cycles. These are responsibilities within the single-cycle core, not pipeline stages separated by registers. Not every value passes through Memory; the writeback diagram shows the bypass paths.

Fetch supplies IMEM_WORD_ADDR/READ_EN and receives IMEM_READ_DATA/FAULT. Memory supplies DMEM_WORD_ADDR/WRITE_DATA/WRITE_MASK/READ_EN/WE and receives DMEM_READ_DATA/FAULT. Combinational port groups translate these stage-local pins into universal byte-addressed REQ/RSP fields. The system connects two zero-wait FF endpoints on the CPU clock. Next PC is a separate selection stage, shown below.

Value Source → destination
Instruction FETCH.INSTRUCTION → DECODE.INSTRUCTION
Current PC FETCH.PC → EXECUTE.PC
Register operands DECODE.RS1_VALUE / RS2_VALUE → EXECUTE
Memory address EXECUTE.ALU_RESULT → MEMORY.ADDR
Store data DECODE.RS2_VALUE → MEMORY.WRITE_DATA

Decode also supplies the immediate and controls for execution, memory access, and writeback. These connections are specified in 4.4.7; the role diagram is not a complete wiring diagram.

Writeback sources

Writeback chooses one source Writeback selects PC plus four, the ALU result, loaded data, or zero and sends WB_VALUE to the register file in Decode. PC + 4 FETCH ALU result EXECUTE Load value MEMORY Zero constant WRITEBACK Select one WB_VALUE DECODE register file
ALU and link results bypass Memory. DECODE.WRITEBACK_SEL selects the source. WB_VALUE is only a candidate: the register file captures it when REGISTER_WRITE permits completion.

Next PC selection

Select a next PC before updating it Next PC selects the fallthrough or branch/jump target using the decoded jump type and branch condition; Fetch owns the PC register. PC + 4 FETCH Control target EXECUTE NEXT_PC Select + check FETCH PC input Selection inputs: DECODE.JUMP_TYPE · EXECUTE.BRANCH_TAKEN
Choosing a PC is not writing the PC. JUMP_TYPE and BRANCH_TAKEN control selection. NEXT_PC checks the active target's alignment; FETCH updates PC only when PC_WRITE is asserted.

Completion control

One edge commits the instruction Execution status combines decode legality, memory faults, and address checks to authorize PC and register updates. It authorizes memory intent before the response; the endpoint itself rejects invalid stores. EXECUTION_STATUS Completion control Decode legality / stop requests Fetch + Memory DONE / FAULT Address checks PC / target / data State writes PC / registers Memory intent prior-fault qualification Terminal state halt / trap / cause
Compute from old state, then capture together. The endpoint validates stores independently: response faults do not feed back into the request opcode. DONE is tied high; the clock period must allow the full path to settle. Clock, reset, and ENABLE are omitted.

EXECUTION_STATUS drives the two stages' ISSUE inputs as direct read/access enables. Memory.COMMIT is tied high: ISSUE excludes prior faults, the stage checks alignment, and the endpoint rejects invalid stores. A response fault must not change the request opcode. DONE is tied high in both direct stages; FAULT and alignment still affect completion. 4.4.7 specifies all control pins and wiring.

State ownership

State Owner When it changes
Architectural PC FETCH.PC_STATE Reset or an authorized completion edge
x1–x31; x0 is constant zero DECODE.REGISTER_FILE Reset or an authorized destination write
Halt/trap flags and cause EXECUTION_STATUS Terminal attempt edge; reset
Instruction/data storage External zero-wait FF endpoints Provisioning before simulation; data writes on the CPU rising edge

Execute, Memory, Writeback, and Next PC are combinational. No stage owns a private instruction/data array. Memory request registers belong to the advanced pipeline's transaction interface, not this single-cycle datapath or the baseline pipeline.

ALU sharing

EXECUTE.ALU performs register/immediate arithmetic, effective-address addition, branch comparisons, LUI/AUIPC, and JAL/JALR target addition. A branch needs comparison and PC+IMM concurrently, so EXECUTE.BRANCH_TARGET_ADD is separate. FETCH.PC_PLUS_4_ADD independently supplies fallthrough and the link value. There is no duplicate RS1+IMM jump adder.

No reading back

An instruction does not modify architectural state and then read that new value to finish itself. Source operands, effective addresses, targets, link values, and store payloads use pre-edge state. On a normal edge, PC, destination register, and any data-memory write capture their already-computed inputs together. Stores have no acknowledgment or read-back phase.

For jalr x5,0(x5) at PC=16 with old x5=24, Execute computes target 24 while Writeback selects link 20. The edge writes PC=24 and x5=20. The updated x5 is not used to compute the target. For lw x1,0(x1), old x1 supplies the address and changes only at the edge after the read has settled.

Modeling boundary

Stage equivalence covers settled binary values and clock-edge state transitions after reset. The catalog attaches gate-derived per-path delays to each behavioral stage. A supported delay twin can time the actual input values; otherwise the table's conservative latest delay applies. The complete core is too large for a delay twin and uses its table. Compact stages do not reproduce every transient gate glitch, and arbitrary X/Z behavior is not claimed equivalent. The examples omit events, delays, and history storage; the per-stage timing notes state the nonbinary limitations. Clock/control/data setup must precede capture. These simulator delays are distinct from the certified clock period and are not calibrated physical timing or a metastability model.