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§ 4.4.2. Decode and Register Read

RV32ISingleCycleDecodeStage decodes the current instruction and owns the core's only architectural register file. It reads both sources continuously and accepts the selected writeback value at the completion edge. In the core it is named DECODE.

Component Description Structural Behavioral
RV32ISingleCycleDecodeStage Instruction controls, two source reads, and one destination write Yes Yes

4.4.2.1. RV32ISingleCycleDecodeStage

IO pins

Pin Direction Width Description
INSTRUCTION Input 32 Current endpoint response word; held through completion by Fetch's protocol
CLK, RST Input 1 each Rising-edge register write; asynchronous active-high reset
REGISTER_WRITE Input 1 Qualified completion write enable, not decoded intent
WB_VALUE Input 32 Value selected by Writeback
RS1_VALUE, RS2_VALUE Output 32 each Values selected from the architectural register file
RS1_ADDR, RS2_ADDR, RD_ADDR Output 5 each Raw instruction fields
IMM Output 32 Constructed immediate
ALU_OP Output 5 ALU32 operation, 0–12 for supported operations
ALU_A_SEL, ALU_B_SEL Output 2 each A: 0 RS1, 1 PC, 2 zero; B: 0 RS2, 1 immediate, 2 zero
LEGAL, REG_WRITE, MEM_READ, MEM_WRITE Output 1 each Legality and decoded update/access intent
WRITEBACK_SEL Output 2 0 none/zero, 1 ALU, 2 load, 3 PC+4
MEM_SIZE Output 2 0 byte, 1 halfword, 2 word/default
LOAD_SIGN_EXTEND Output 1 Signed byte/halfword load
USES_RS1, USES_RS2 Output 1 each Whether the corresponding raw field is an instruction dependency
BRANCH_TYPE Output 3 0 none, 1 EQ, 2 NE, 3 signed LT, 4 signed GE, 5 unsigned LT, 6 unsigned GE
JUMP_TYPE Output 2 0 none, 1 JAL, 2 JALR
HALT_REQUEST, TRAP_REQUEST Output 1 each Decoded terminal intent
DECODE_TRAP_CAUSE Output 4 0 none, 1 illegal instruction, 2 ECALL; project codes

Behavior

All decoder outputs follow the complete recognition, immediate, and fallback rules in 4.3.4. They are not latched here. Source and destination addresses remain raw fields even when an instruction does not use them. Both source outputs still read their raw addresses; USES_RS1/2 describes dependency, not read gating.

Reset clears x1–x31; x0 is always zero. On a rising edge, REGISTER_WRITE=1 writes WB_VALUE to the current instruction's nonzero RD_ADDR. This input is already qualified by execution status. Decode does not internally AND it with LEGAL or REG_WRITE: those are separately exposed intent outputs. The core is responsible for suppressing writes on stalls and faults.

There is no WB-to-read bypass. If the destination is also a source, reads show old storage before capture and updated storage after capture/propagation. Changing WB_VALUE while CLK remains high does not write again. Decode contains neither an instruction register nor a pipeline hazard/forwarding unit.

C++ example

Reuse decode_example::Decoded and decode_example::decode from 4.3.4. Inheritance below forwards every decoder output; only the two register-value fields are added. This is the binary, post-reset model of the register-file contract, not a redefinition of instruction decoding.

#include <array>
#include <cstdint>
namespace single_cycle_example {
struct DecodeInputs {
    uint32_t INSTRUCTION;
    bool CLK, RST, REGISTER_WRITE;
    uint32_t WB_VALUE;
};
struct DecodeOutputs : decode_example::Decoded {
    uint32_t RS1_VALUE=0, RS2_VALUE=0;
};
class Decode {
    std::array<uint32_t,32> registers{};
    bool previous_clock=false;
public:
    DecodeOutputs observe(const DecodeInputs& i) const {
        const auto d=decode_example::decode(i.INSTRUCTION);
        DecodeOutputs out;
        static_cast<decode_example::Decoded&>(out)=d;
        out.RS1_VALUE=registers[d.RS1_ADDR];
        out.RS2_VALUE=registers[d.RS2_ADDR];
        return out;
    }
    DecodeOutputs evaluate(const DecodeInputs& i) {
        const unsigned rd=(i.INSTRUCTION>>7)&31;
        if (i.RST) registers.fill(0);
        else if (!previous_clock && i.CLK && i.REGISTER_WRITE && rd!=0)
            registers[rd]=i.WB_VALUE;
        previous_clock=i.CLK;
        return observe(i);
    }
    const std::array<uint32_t,32>& state() const { return registers; }
};
}

Unknown inputs and timing

Real simulator x1–x31 start unknown until reset; the simplified array is only a post-reset reference. Structural nonbinary behavior follows the decoder and register-file children. The behavioral stage makes all outputs unknown for a nonbinary instruction, but still updates its register file from instruction bits 11:7, REGISTER_WRITE, WB_VALUE, reset, and the clock. An uncertain destination can therefore affect multiple candidate registers under the register-file rules; a known enabled write copies the WB bit vector, with captured Z becoming X. Only known low-to-high clock transitions capture writes. Binary stage equivalence remains the checked scope. Catalog-selected outputs use gate-derived path and clock-to-output delays; recorded register history becomes visible when the scheduled output is published, not retroactively.

Implementation

Structural implementation

CONTROL is RV32IDecodeControlUnit; REGISTER_FILE is RegisterFile32x32. Raw addresses connect to the register file, WB_VALUE to its write-data input, and REGISTER_WRITE to its write enable. The register file reuses the FF bank/word/cell hierarchy from chapter 3. No second copy of its storage is kept in the stage.

Behavioral implementation

BehavioralDecodeStage uses the direct stage evaluator, a 32-word four-state register vector, and timestamped register snapshots. It computes controls through RV32IDecoder/RV32IControl and implements writes on known rising edges. Both implementations expose register-state-view so the visualizer can inspect registers without depending on the internal hierarchy. The family is rv32i.single-cycle.decode.

Examples

The scenario reuses every decoder vector, then checks register setup without bypass, edge-only capture, high/falling-clock holds, ignored x0 writes, and reset. For example, setting WB_VALUE=7 and write enable does not change x1 until the capture edge.

All 126 recorded rows of RV32ISingleCycleDecodeStageTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (6deabf16f44713f8). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label Timesimulator units CLKInput · 1 bit INSTRUCTIONInput · 32 bit REGISTER_WRITEInput · 1 bit RSTInput · 1 bit WB_VALUEInput · 32 bit ALU_A_SELExpected output · 2 bit ALU_B_SELExpected output · 2 bit ALU_OPExpected output · 5 bit BRANCH_TYPEExpected output · 3 bit DECODE_TRAP_CAUSEExpected output · 4 bit HALT_REQUESTExpected output · 1 bit IMMExpected output · 32 bit JUMP_TYPEExpected output · 2 bit LEGALExpected output · 1 bit LOAD_SIGN_EXTENDExpected output · 1 bit MEM_READExpected output · 1 bit MEM_SIZEExpected output · 2 bit MEM_WRITEExpected output · 1 bit RD_ADDRExpected output · 5 bit REG_WRITEExpected output · 1 bit RS1_ADDRExpected output · 5 bit RS1_VALUEExpected output · 32 bit RS2_ADDRExpected output · 5 bit RS2_VALUEExpected output · 32 bit TRAP_REQUESTExpected output · 1 bit USES_RS1Expected output · 1 bit USES_RS2Expected output · 1 bit WRITEBACK_SELExpected output · 2 bit
#0reset15 0 0x00000000 0 1 0x00000000 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0x00000000 not checked 0x00000000 not checked not checked not checked not checked
#1release16 0 0x00000000 0 0 0x00000000 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#2add35 0 0x00C58533 0 0 0x00000000 0x0 0x0 0x00 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#3subtract45 0 0x40C58533 0 0 0x00000000 0x0 0x0 0x01 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#4shift-left-logical59 0 0x00C59533 0 0 0x00000000 0x0 0x0 0x05 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#5set-less-than73 0 0x00C5A533 0 0 0x00000000 0x0 0x0 0x08 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#6set-less-than-unsigned83 0 0x00C5B533 0 0 0x00000000 0x0 0x0 0x09 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#7exclusive-or97 0 0x00C5C533 0 0 0x00000000 0x0 0x0 0x04 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#8shift-right-logical107 0 0x00C5D533 0 0 0x00000000 0x0 0x0 0x06 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#9shift-right-arithmetic117 0 0x40C5D533 0 0 0x00000000 0x0 0x0 0x07 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#10or131 0 0x00C5E533 0 0 0x00000000 0x0 0x0 0x03 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#11and142 0 0x00C5F533 0 0 0x00000000 0x0 0x0 0x02 0x0 0x0 0 0x00000000 0x0 1 0 0 0x2 0 0x0A 1 0x0B not checked 0x0C not checked 0 1 1 0x1
#12add-immediate161 0 0xFFF28313 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0xFFFFFFFF 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x1F not checked 0 1 0 0x1
#13set-less-than-immediate174 0 0x8002A313 0 0 0x00000000 0x0 0x1 0x08 0x0 0x0 0 0xFFFFF800 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x00 not checked 0 1 0 0x1
#14set-less-than-immediate-unsigned187 0 0x7FF2B313 0 0 0x00000000 0x0 0x1 0x09 0x0 0x0 0 0x000007FF 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x1F not checked 0 1 0 0x1
#15exclusive-or-immediate205 0 0x0552C313 0 0 0x00000000 0x0 0x1 0x04 0x0 0x0 0 0x00000055 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x15 not checked 0 1 0 0x1
#16or-immediate218 0 0x1232E313 0 0 0x00000000 0x0 0x1 0x03 0x0 0x0 0 0x00000123 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x03 not checked 0 1 0 0x1
#17and-immediate231 0 0x3212F313 0 0 0x00000000 0x0 0x1 0x02 0x0 0x0 0 0x00000321 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x01 not checked 0 1 0 0x1
#18shift-left-logical-immediate250 0 0x00529313 0 0 0x00000000 0x0 0x1 0x05 0x0 0x0 0 0x00000005 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x05 not checked 0 1 0 0x1
#19shift-right-logical-immediate263 0 0x0062D313 0 0 0x00000000 0x0 0x1 0x06 0x0 0x0 0 0x00000006 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x06 not checked 0 1 0 0x1
#20shift-right-arithmetic-immediate276 0 0x41F2D313 0 0 0x00000000 0x0 0x1 0x07 0x0 0x0 0 0x0000041F 0x0 1 0 0 0x2 0 0x06 1 0x05 not checked 0x1F not checked 0 1 0 0x1
#21load-byte295 0 0xFF018203 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0xFFFFFFF0 0x0 1 1 1 0x0 0 0x04 1 0x03 not checked 0x10 not checked 0 1 0 0x2
#22load-halfword308 0 0x01219203 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0x00000012 0x0 1 1 1 0x1 0 0x04 1 0x03 not checked 0x12 not checked 0 1 0 0x2
#23load-word326 0 0x0141A203 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0x00000014 0x0 1 0 1 0x2 0 0x04 1 0x03 not checked 0x14 not checked 0 1 0 0x2
#24load-byte-unsigned344 0 0x0151C203 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0x00000015 0x0 1 0 1 0x0 0 0x04 1 0x03 not checked 0x15 not checked 0 1 0 0x2
#25load-halfword-unsigned357 0 0x0161D203 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0x00000016 0x0 1 0 1 0x1 0 0x04 1 0x03 not checked 0x16 not checked 0 1 0 0x2
#26store-byte377 0 0xFE838623 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0xFFFFFFEC 0x0 1 0 0 0x0 1 0x0C 0 0x07 not checked 0x08 not checked 0 1 1 0x0
#27store-halfword385 0 0x00839C23 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0x00000018 0x0 1 0 0 0x1 1 0x18 0 0x07 not checked 0x08 not checked 0 1 1 0x0
#28store-word400 0 0x0083AE23 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0x0000001C 0x0 1 0 0 0x2 1 0x1C 0 0x07 not checked 0x08 not checked 0 1 1 0x0
#29branch-equal416 0 0x00208863 0 0 0x00000000 0x0 0x0 0x01 0x1 0x0 0 0x00000010 0x0 1 0 0 0x2 0 0x10 0 0x01 not checked 0x02 not checked 0 1 1 0x0
#30branch-not-equal426 0 0xFE209EE3 0 0 0x00000000 0x0 0x0 0x01 0x2 0x0 0 0xFFFFFFFC 0x0 1 0 0 0x2 0 0x1D 0 0x01 not checked 0x02 not checked 0 1 1 0x0
#31branch-less-than444 0 0x0220C063 0 0 0x00000000 0x0 0x0 0x01 0x3 0x0 0 0x00000020 0x0 1 0 0 0x2 0 0x00 0 0x01 not checked 0x02 not checked 0 1 1 0x0
#32branch-greater-or-equal455 0 0xFE20D0E3 0 0 0x00000000 0x0 0x0 0x01 0x4 0x0 0 0xFFFFFFE0 0x0 1 0 0 0x2 0 0x01 0 0x01 not checked 0x02 not checked 0 1 1 0x0
#33branch-less-than-unsigned473 0 0x0420E063 0 0 0x00000000 0x0 0x0 0x01 0x5 0x0 0 0x00000040 0x0 1 0 0 0x2 0 0x00 0 0x01 not checked 0x02 not checked 0 1 1 0x0
#34branch-greater-or-equal-unsigned485 0 0xFC20F0E3 0 0 0x00000000 0x0 0x0 0x01 0x6 0x0 0 0xFFFFFFC0 0x0 1 0 0 0x2 0 0x01 0 0x01 not checked 0x02 not checked 0 1 1 0x0
#35jump-and-link502 0 0x800002EF 0 0 0x00000000 0x1 0x1 0x00 0x0 0x0 0 0xFFF00000 0x1 1 0 0 0x2 0 0x05 1 0x00 not checked 0x00 not checked 0 0 0 0x3
#36jump-and-link-register521 0 0xFF4280E7 0 0 0x00000000 0x0 0x1 0x00 0x0 0x0 0 0xFFFFFFF4 0x2 1 0 0 0x2 0 0x01 1 0x05 not checked 0x14 not checked 0 1 0 0x3
#37load-upper-immediate539 0 0x123454B7 0 0 0x00000000 0x2 0x1 0x0B 0x0 0x0 0 0x12345000 0x0 1 0 0 0x2 0 0x09 1 0x08 not checked 0x03 not checked 0 0 0 0x1
#38add-upper-immediate-to-pc552 0 0xFFFFF497 0 0 0x00000000 0x1 0x1 0x00 0x0 0x0 0 0xFFFFF000 0x0 1 0 0 0x2 0 0x09 1 0x1F not checked 0x1F not checked 0 0 0 0x1
#39fence571 0 0x0FF0000F 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x0 0 0x000000FF 0x0 1 0 0 0x2 0 0x00 0 0x00 not checked 0x1F not checked 0 0 0 0x0
#40environment-call587 0 0x00000073 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x2 0 0x00000000 0x0 1 0 0 0x2 0 0x00 0 0x00 not checked 0x00 not checked 1 0 0 0x0
#41breakpoint600 0 0x00100073 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x0 1 0x00000001 0x0 1 0 0 0x2 0 0x00 0 0x00 not checked 0x01 not checked 0 0 0 0x0
#42illegal-instruction-length613 0 0x00000000 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x00 not checked 0x00 not checked 1 0 0 0x0
#43illegal-unknown-opcode629 0 0x0000007B 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x00 not checked 0x00 not checked 1 0 0 0x0
#44illegal-rv64-op-immediate642 0 0x0000811B 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x02 0 0x01 not checked 0x00 not checked 1 0 0 0x0
#45illegal-register-funct7655 0 0x022081B3 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x03 0 0x01 not checked 0x02 not checked 1 0 0 0x0
#46illegal-shift-funct7668 0 0x0250D113 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x02 0 0x01 not checked 0x05 not checked 1 0 0 0x0
#47illegal-branch-funct3681 0 0x0020A263 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x04 0 0x01 not checked 0x02 not checked 1 0 0 0x0
#48illegal-load-funct3694 0 0x0000B103 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x02 0 0x01 not checked 0x00 not checked 1 0 0 0x0
#49illegal-store-funct3707 0 0x0020B023 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x01 not checked 0x02 not checked 1 0 0 0x0
#50illegal-jalr-funct3726 0 0x00009167 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x02 0 0x01 not checked 0x00 not checked 1 0 0 0x0
#51illegal-fence-i739 0 0x0000100F 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x00 not checked 0x00 not checked 1 0 0 0x0
#52illegal-csr752 0 0x00101073 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x00 not checked 0x01 not checked 1 0 0 0x0
#53illegal-system-operation765 0 0x00200073 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x00 not checked 0x02 not checked 1 0 0 0x0
#54deterministic-raw-0778 0 0x06B0B208 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x04 0 0x01 not checked 0x0B not checked 1 0 0 0x0
#55deterministic-raw-1791 0 0x5D1F2DC7 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1B 0 0x1E not checked 0x11 not checked 1 0 0 0x0
#56deterministic-raw-2804 0 0xDBB0907A 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x00 0 0x01 not checked 0x1B not checked 1 0 0 0x0
#57deterministic-raw-3817 0 0xD9E0E591 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x0B 0 0x01 not checked 0x1E not checked 1 0 0 0x0
#58deterministic-raw-4830 0 0x537B61BC 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x03 0 0x16 not checked 0x17 not checked 1 0 0 0x0
#59deterministic-raw-5843 0 0x2DFFD1EB 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x03 0 0x1F not checked 0x1F not checked 1 0 0 0x0
#60deterministic-raw-6856 0 0x00033E4E 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1C 0 0x06 not checked 0x00 not checked 1 0 0 0x0
#61deterministic-raw-7869 0 0x9D0A3155 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x02 0 0x14 not checked 0x10 not checked 1 0 0 0x0
#62deterministic-raw-8882 0 0x16E852B0 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x05 0 0x10 not checked 0x0E not checked 1 0 0 0x0
#63deterministic-raw-9895 0 0x0A5D464F 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x0C 0 0x1A not checked 0x05 not checked 1 0 0 0x0
#64deterministic-raw-10908 0 0xCAE5FF62 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1E 0 0x0B not checked 0x0E not checked 1 0 0 0x0
#65deterministic-raw-11921 0 0x1E6FF759 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x0E 0 0x1F not checked 0x06 not checked 1 0 0 0x0
#66deterministic-raw-12934 0 0x8C5CF8E4 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x11 0 0x19 not checked 0x05 not checked 1 0 0 0x0
#67deterministic-raw-13947 0 0xB6966EF3 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1D 0 0x0C not checked 0x09 not checked 1 0 0 0x0
#68deterministic-raw-14960 0 0x480267B6 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x0F 0 0x04 not checked 0x00 not checked 1 0 0 0x0
#69deterministic-raw-15973 0 0xFAA6BB9D 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x17 0 0x0D not checked 0x0A not checked 1 0 0 0x0
#70deterministic-raw-16986 0 0xB7FC0858 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x10 0 0x18 not checked 0x1F not checked 1 0 0 0x0
#71deterministic-raw-17999 0 0xD0266FD7 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1F 0 0x0C not checked 0x02 not checked 1 0 0 0x0
#72deterministic-raw-181012 0 0x0AF14B4A 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x16 0 0x02 not checked 0x0F not checked 1 0 0 0x0
#73deterministic-raw-191025 0 0x48E94221 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x04 0 0x12 not checked 0x0E not checked 1 0 0 0x0
#74deterministic-raw-201038 0 0x55D9750C 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x0A 0 0x12 not checked 0x1D not checked 1 0 0 0x0
#75deterministic-raw-211051 0 0xAB48ACFB 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x19 0 0x11 not checked 0x14 not checked 1 0 0 0x0
#76deterministic-raw-221064 0 0xC88EBE1E 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1C 0 0x1D not checked 0x08 not checked 1 0 0 0x0
#77deterministic-raw-231077 0 0xDC5C8EE5 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x1D 0 0x19 not checked 0x05 not checked 1 0 0 0x0
#78deterministic-raw-241090 0 0x426E7300 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x06 0 0x1C not checked 0x06 not checked 1 0 0 0x0
#79deterministic-raw-251103 0 0xD8DCCA5F 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x14 0 0x19 not checked 0x0D not checked 1 0 0 0x0
#80deterministic-raw-261116 0 0xFB8E1432 0 0 0x00000000 0x2 0x2 0x0C 0x0 0x1 0 0x00000000 0x0 0 0 0 0x2 0 0x08 0 0x1C not checked 0x18 not checked 1 0 0 0x0
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Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open Decode stage

Tests

RV32ISingleCycleDecodeStageTest compares both implementations, including every forwarded control. RV32ISingleCycleStageIntegrationTest exercises overlapping source/destination registers and unchanged registers during memory waits. Native/WASM parity checks also inspect register history. RV32ISingleCycleDocumentationTest.py verifies this table and replays the exact example. Source: RV32ISingleCycleStages.cpp and RV32ISingleCycleStagesBehavioral.cpp; scenarios: src/tests/RV32ISingleCycleStageTests.cpp.