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§ 4.1. RV32I Reference

The instruction-level specification and executable answer sheet for CircuitSim's RV32I core. The single-cycle and five-stage cores must agree on the ordered register, memory, PC, and terminal effects defined here; their internal circuits and timing may differ.

Hardware component interfaces and implementations are documented separately in 4.3. RV32I Building Blocks.

Contents

Section Contents
4.1.1. Machine model and common conventions State, numeric and memory rules, common exceptions, register names, and stack conventions
4.1.2. Instruction formats and decoding Field positions, immediate reconstruction, selection rules, and invalid encodings
4.1.3. Instruction reference All 40 instructions, each with syntax, encoding, operands, operation, exceptions, and an example
4.1.4. Executable RV32I reference Architectural state, instruction-step API, complete behavioral implementation, and a runnable example

Programs and verification are documented in 4.2. Benchmarking and Verification, including all 22 fixed programs, generated workloads, compiled workloads, and the shared measurement contract. The one-step instruction examples remain with the executable reference above.

Instruction families

Family Instructions
Arithmetic ADD, SUB, ADDI
Logic AND, OR, XOR, ANDI, ORI, XORI
Shifts SLL, SRL, SRA, SLLI, SRLI, SRAI
Comparisons SLT, SLTU, SLTI, SLTIU
Upper Immediates LUI, AUIPC
Loads LB, LH, LW, LBU, LHU
Stores SB, SH, SW
Branches BEQ, BNE, BLT, BGE, BLTU, BGEU
Jumps JAL, JALR
Ordering and System FENCE, ECALL, EBREAK

Scope and authorities

The scope is the 40 instructions of RV32I version 2.1, with CircuitSim's explicitly documented execution-environment choices. Extensions and privileged machinery are outside this reference.

The instruction catalogue is the primary lookup view. ISA rules, simulator policies, and software conventions are distinguished throughout.