Program 7: Fibonacci sequence

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Purpose

Generate and store the first eight Fibonacci values using a loop and register copies.

This is an instruction-behavior correctness fixture.

Setup

Property	Value
Benchmark workload ID	program-07
Headless selection	--program 7
Visualizer scenario	rv32i-program7
Registered test	RV32ISingleCycleSystemTest/program-07
Instruction image	12 words, starting at 0x00000000; last word at 0x0000002C
Initial state	PC = 0x00000000; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
x1	Next output address
x2	Remaining output count
x3	Current Fibonacci value a
x4	Next value b
x5	Temporary a+b

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

addi x1, x0, 0x120             # 0x00000000 | 0x12000093
addi x2, x0, 8                 # 0x00000004 | 0x00800113
addi x3, x0, 0                 # 0x00000008 | 0x00000193
addi x4, x0, 1                 # 0x0000000C | 0x00100213
fib_loop:
sw x3, 0(x1)                   # 0x00000010 | 0x0030A023
add x5, x3, x4                 # 0x00000014 | 0x004182B3
addi x3, x4, 0                 # 0x00000018 | 0x00020193
addi x4, x5, 0                 # 0x0000001C | 0x00028213
addi x1, x1, 4                 # 0x00000020 | 0x00408093
addi x2, x2, -1                # 0x00000024 | 0xFFF10113
bne x2, x0, fib_loop           # 0x00000028 | 0xFE0114E3
ebreak                         # 0x0000002C | 0x00100073

Execution

1. Initialize the destination to 0x120, count to eight, and pair (a,b) to (0,1).
2. Each iteration stores the old a, computes a+b, then updates the pair to (b,a+b). ADDI with immediate zero performs the register copies.
3. Advance the output pointer by four bytes, decrement the count, and repeat while nonzero.
4. The eight stored words are 0, 1, 1, 2, 3, 5, 8, 13. The final register pair is (21,34) because the update still happens after storing the eighth value.
5. Halt after 4 + 8 × 7 + 1 = 61 attempts. The pointer ends at 0x140, just past the output array.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
x1	0x00000140	Next output address
x2	0x00000000	Remaining output count
x3	0x00000015	Current Fibonacci value a
x4	0x00000022	Next value b
PC	0x0000002C	EBREAK address
Attempts	61	Checkpoints I0–I60
HALTED	1	Project halt
TRAPPED	0	No exception
TRAP_CAUSE	0	None, a project enum code

Start address	Bytes, in increasing address order
0x00000120	00 00 00 00
0x00000124	01 00 00 00
0x00000128	01 00 00 00
0x0000012C	02 00 00 00
0x00000130	03 00 00 00
0x00000134	05 00 00 00
0x00000138	08 00 00 00
0x0000013C	0D 00 00 00

All data bytes not listed as written retain their initial values. The final x3/x4 values are the next pair, not the last two stored words.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 7 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 61 instruction attempts are included, with absolute simulator time and checkpoint number. The terminating EBREAK is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 61 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-07, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7080	ADDI @ 0x00000000	raw=0x12000093, pc_after=0x00000004, wb=x1=0x00000120, mem=None, flow=next
I1	11080	ADDI @ 0x00000004	raw=0x00800113, pc_after=0x00000008, wb=x2=0x00000008, mem=None, flow=next
I2	15080	ADDI @ 0x00000008	raw=0x00000193, pc_after=0x0000000c, wb=x3=0x00000000, mem=None, flow=next
I3	19080	ADDI @ 0x0000000c	raw=0x00100213, pc_after=0x00000010, wb=x4=0x00000001, mem=None, flow=next
I4	23080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x00000120 <- 0x00000000, flow=next
I5	27080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000001, mem=None, flow=next
I6	31080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000001, mem=None, flow=next
I7	35080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000001, mem=None, flow=next
I8	39080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x00000124, mem=None, flow=next
I9	43080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000007, mem=None, flow=next
I10	47080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I11	51080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x00000124 <- 0x00000001, flow=next
I12	55080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000002, mem=None, flow=next
I13	59080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000001, mem=None, flow=next
I14	63080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000002, mem=None, flow=next
I15	67080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x00000128, mem=None, flow=next
I16	71080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000006, mem=None, flow=next
I17	75080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I18	79080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x00000128 <- 0x00000001, flow=next
I19	83080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000003, mem=None, flow=next
I20	87080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000002, mem=None, flow=next
I21	91080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000003, mem=None, flow=next
I22	95080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x0000012c, mem=None, flow=next
I23	99080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000005, mem=None, flow=next
I24	103080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I25	107080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x0000012c <- 0x00000002, flow=next
I26	111080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000005, mem=None, flow=next
I27	115080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000003, mem=None, flow=next
I28	119080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000005, mem=None, flow=next
I29	123080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x00000130, mem=None, flow=next
I30	127080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000004, mem=None, flow=next
I31	131080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I32	135080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x00000130 <- 0x00000003, flow=next
I33	139080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000008, mem=None, flow=next
I34	143080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000005, mem=None, flow=next
I35	147080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000008, mem=None, flow=next
I36	151080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x00000134, mem=None, flow=next
I37	155080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000003, mem=None, flow=next
I38	159080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I39	163080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x00000134 <- 0x00000005, flow=next
I40	167080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x0000000d, mem=None, flow=next
I41	171080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000008, mem=None, flow=next
I42	175080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x0000000d, mem=None, flow=next
I43	179080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x00000138, mem=None, flow=next
I44	183080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000002, mem=None, flow=next
I45	187080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I46	191080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x00000138 <- 0x00000008, flow=next
I47	195080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000015, mem=None, flow=next
I48	199080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x0000000d, mem=None, flow=next
I49	203080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000015, mem=None, flow=next
I50	207080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x0000013c, mem=None, flow=next
I51	211080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000001, mem=None, flow=next
I52	215080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x00000010, wb=None, mem=None, branch=BNE taken=true
I53	219080	SW @ 0x00000010	raw=0x0030a023, pc_after=0x00000014, wb=None, mem=Write Word @0x0000013c <- 0x0000000d, flow=next
I54	223080	ADD @ 0x00000014	raw=0x004182b3, pc_after=0x00000018, wb=x5=0x00000022, mem=None, flow=next
I55	227080	ADDI @ 0x00000018	raw=0x00020193, pc_after=0x0000001c, wb=x3=0x00000015, mem=None, flow=next
I56	231080	ADDI @ 0x0000001c	raw=0x00028213, pc_after=0x00000020, wb=x4=0x00000022, mem=None, flow=next
I57	235080	ADDI @ 0x00000020	raw=0x00408093, pc_after=0x00000024, wb=x1=0x00000140, mem=None, flow=next
I58	239080	ADDI @ 0x00000024	raw=0xfff10113, pc_after=0x00000028, wb=x2=0x00000000, mem=None, flow=next
I59	243080	BNE @ 0x00000028	raw=0xfe0114e3, pc_after=0x0000002c, wb=None, mem=None, branch=BNE taken=false
I60	247080	EBREAK @ 0x0000002c	raw=0x00100073, pc_after=0x0000002c, wb=None, mem=None, flow=next, halted=true

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