§ 4.5.7. Dependencies and Control

The baseline has two separate control components: one detects unavailable register operands; the other decides which pipeline registers hold, advance, or receive bubbles. Neither stores an instruction or predicts a branch.

Component	Description	Structural	Behavioral
RV32IBaselineDependencyUnit	RAW dependencies against three older instruction slots	Yes	Yes
RV32IBaselineControl	Enable, stall, bubble, branch-wait and terminal arbitration	Yes	Yes
RV32IBaselinePacketStatus	Internal shared packet-status gate group	Yes	No standalone variant

HALTED and TRAPPED come from the separate execution-status block, not storage inside Writeback. They keep control inactive after the terminal packet leaves MEM/WB.

Control responsibilities

CONTROL is the main coordinator: it decides how instructions move, but does not calculate register results or jump addresses. Detection, calculation, and state updates remain separate jobs.

Child in the complete core	Responsibility
DEPENDENCIES	Report whether Decode needs a register value that an older instruction has not written yet
DECODE	Identify source registers and recognize branches/jumps
EXECUTE.DATAPATH and EXECUTE.NEXT_PC	Evaluate the branch condition and calculate/select the resolved next address
CONTROL	Decide which pipeline registers hold, advance, or receive bubbles, and when Fetch may update its PC
FETCH and the four pipeline registers	Carry out those decisions at the clock edge

The CONTROL child inside DECODE is the instruction decoder, not this top-level pipeline coordinator. In the visualizer, inspect the complete core's DEPENDENCIES and CONTROL blocks for hazard handling.

4.5.7.1. RV32IBaselineDependencyUnit

IO pins

Pin	Direction	Width	Description
D_VALID, E_VALID, M_VALID, W_VALID	Input	1 each	Decode/Execute/Memory/Writeback validity
D_CONTROL, E_CONTROL, M_CONTROL, W_CONTROL	Input	32 each	Packed decoded control
D_REGISTER_ADDRESSES, E_REGISTER_ADDRESSES, M_REGISTER_ADDRESSES, W_REGISTER_ADDRESSES	Input	32 each	Packed register addresses
WAIT_EX, WAIT_MEM, WAIT_WB	Output	1 each	At least one actually used source depends on that older slot
DATA_HAZARD	Output	1	OR of the three wait outputs

Behavior

A match requires a valid consumer, a valid producer with REG_WRITE=1 and RD≠0, and a matching source whose USES_RS bit is one. Encoded but unused source bits do not cause a stall. x0 never produces a dependency. All older writers matter, not only loads.

The comparisons use register numbers, not register values: “Decode reads x1, and an older instruction will write x1.” WAIT_EX, WAIT_MEM, and WAIT_WB check the three older slots independently; their OR is DATA_HAZARD. The detector reports the conflict; it does not hold registers itself.

WAIT_WB deliberately includes a producer currently in WB. Without a bypass, the old register value is still present before that producer's edge. An immediately dependent instruction normally waits three cycles: producer in EX, then MEM, then WB.

C++ example

inline bool waits_for(const Packet& decode,const Packet& producer) {
    const auto destination=rd(producer.addresses);
    return decode.valid && producer.valid && bits(producer.control,1,1) && destination &&
        ((bits(decode.control,7,1)&&rs1(decode.addresses)==destination) ||
         (bits(decode.control,8,1)&&rs2(decode.addresses)==destination));
}
struct Dependency { bool wait_ex,wait_mem,wait_wb,data_hazard; };
inline Dependency dependency(const Packet& d,const Packet& e,const Packet& m,const Packet& w) {
    const bool ex=waits_for(d,e),mem=waits_for(d,m),wb=waits_for(d,w);
    return {ex,mem,wb,ex||mem||wb};
}

Implementation

Structural implementation

DECODE_FIELDS/SOURCE_REGISTERS unpack the consumer. WAIT_EX, WAIT_MEM, and WAIT_WB reuse the tested two-source comparison circuit in RV32IHazardDetectionUnit. That older component names its producer-enable pin EX_MEM_READ; here REG_WRITE drives it so the comparator checks all register producers. This reuse does not turn the baseline into a load-only hazard detector.

Behavioral implementation

Three independent register-match checks produce the same outputs. The registered family is rv32i.baseline.dependency.

Examples

Every destination register, including x0, is tested in each producer position, followed by disabled/bubble producers and ignored sources.

All 106 recorded rows of RV32IBaselineDependencyUnitTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: baseline-structural-stages / structural (f72af366c5dca6eb). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	D_CONTROLInput · 32 bit	D_REGISTER_ADDRESSESInput · 32 bit	D_VALIDInput · 1 bit	E_CONTROLInput · 32 bit	E_REGISTER_ADDRESSESInput · 32 bit	E_VALIDInput · 1 bit	M_CONTROLInput · 32 bit	M_REGISTER_ADDRESSESInput · 32 bit	M_VALIDInput · 1 bit	W_CONTROLInput · 32 bit	W_REGISTER_ADDRESSESInput · 32 bit	W_VALIDInput · 1 bit	DATA_HAZARDExpected output · 1 bit	WAIT_EXExpected output · 1 bit	WAIT_MEMExpected output · 1 bit	WAIT_WBExpected output · 1 bit
#0initial-inputs	7	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0x00000000	0x00000000	0	not checked	not checked	not checked	not checked
#1two-sources	17	0x00000180	0x00000041	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0x00000000	0x00000000	0	not checked	not checked	not checked	not checked
#2E-destination-0	20	0x00000180	0x00000041	1	0x00000002	0x00000000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#3E-destination-1	32	0x00000180	0x00000041	1	0x00000002	0x00000400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	1	1	not checked	not checked
#4E-destination-2	41	0x00000180	0x00000041	1	0x00000002	0x00000800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	1	1	not checked	not checked
#5E-destination-3	53	0x00000180	0x00000041	1	0x00000002	0x00000C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#6E-destination-4	59	0x00000180	0x00000041	1	0x00000002	0x00001000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#7E-destination-5	65	0x00000180	0x00000041	1	0x00000002	0x00001400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#8E-destination-6	71	0x00000180	0x00000041	1	0x00000002	0x00001800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#9E-destination-7	77	0x00000180	0x00000041	1	0x00000002	0x00001C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#10E-destination-8	82	0x00000180	0x00000041	1	0x00000002	0x00002000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#11E-destination-9	88	0x00000180	0x00000041	1	0x00000002	0x00002400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#12E-destination-10	94	0x00000180	0x00000041	1	0x00000002	0x00002800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#13E-destination-11	100	0x00000180	0x00000041	1	0x00000002	0x00002C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#14E-destination-12	105	0x00000180	0x00000041	1	0x00000002	0x00003000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#15E-destination-13	111	0x00000180	0x00000041	1	0x00000002	0x00003400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#16E-destination-14	117	0x00000180	0x00000041	1	0x00000002	0x00003800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#17E-destination-15	123	0x00000180	0x00000041	1	0x00000002	0x00003C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#18E-destination-16	129	0x00000180	0x00000041	1	0x00000002	0x00004000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#19E-destination-17	136	0x00000180	0x00000041	1	0x00000002	0x00004400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#20E-destination-18	143	0x00000180	0x00000041	1	0x00000002	0x00004800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#21E-destination-19	150	0x00000180	0x00000041	1	0x00000002	0x00004C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#22E-destination-20	156	0x00000180	0x00000041	1	0x00000002	0x00005000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#23E-destination-21	162	0x00000180	0x00000041	1	0x00000002	0x00005400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#24E-destination-22	168	0x00000180	0x00000041	1	0x00000002	0x00005800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#25E-destination-23	174	0x00000180	0x00000041	1	0x00000002	0x00005C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#26E-destination-24	179	0x00000180	0x00000041	1	0x00000002	0x00006000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#27E-destination-25	185	0x00000180	0x00000041	1	0x00000002	0x00006400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#28E-destination-26	191	0x00000180	0x00000041	1	0x00000002	0x00006800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#29E-destination-27	197	0x00000180	0x00000041	1	0x00000002	0x00006C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#30E-destination-28	202	0x00000180	0x00000041	1	0x00000002	0x00007000	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#31E-destination-29	208	0x00000180	0x00000041	1	0x00000002	0x00007400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#32E-destination-30	214	0x00000180	0x00000041	1	0x00000002	0x00007800	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#33E-destination-31	220	0x00000180	0x00000041	1	0x00000002	0x00007C00	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	0	not checked	not checked
#34E-disabled-producer	230	0x00000180	0x00000041	1	0x00000000	0x00000400	1	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	not checked	not checked	not checked
#35E-bubble	233	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000000	0x00000000	0	0x00000000	0x00000000	0	0	not checked	not checked	not checked
#36M-destination-0	236	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#37M-destination-1	248	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	1	0x00000000	0x00000000	0	1	not checked	1	not checked
#38M-destination-2	257	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000800	1	0x00000000	0x00000000	0	1	not checked	1	not checked
#39M-destination-3	269	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#40M-destination-4	275	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00001000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#41M-destination-5	281	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00001400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#42M-destination-6	287	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00001800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#43M-destination-7	293	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00001C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#44M-destination-8	298	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00002000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#45M-destination-9	304	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00002400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#46M-destination-10	310	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00002800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#47M-destination-11	316	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00002C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#48M-destination-12	321	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00003000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#49M-destination-13	327	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00003400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#50M-destination-14	333	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00003800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#51M-destination-15	339	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00003C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#52M-destination-16	345	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00004000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#53M-destination-17	352	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00004400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#54M-destination-18	359	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00004800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#55M-destination-19	366	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00004C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#56M-destination-20	372	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00005000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#57M-destination-21	378	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00005400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#58M-destination-22	384	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00005800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#59M-destination-23	390	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00005C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#60M-destination-24	395	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00006000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#61M-destination-25	401	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00006400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#62M-destination-26	407	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00006800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#63M-destination-27	413	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00006C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#64M-destination-28	418	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00007000	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#65M-destination-29	424	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00007400	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#66M-destination-30	430	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00007800	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#67M-destination-31	436	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00007C00	1	0x00000000	0x00000000	0	0	not checked	0	not checked
#68M-disabled-producer	446	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000000	0x00000400	1	0x00000000	0x00000000	0	0	not checked	not checked	not checked
#69M-bubble	449	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000000	0x00000000	0	0	not checked	not checked	not checked
#70W-destination-0	452	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00000000	1	0	not checked	not checked	0
#71W-destination-1	463	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00000400	1	1	not checked	not checked	1
#72W-destination-2	472	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00000800	1	1	not checked	not checked	1
#73W-destination-3	483	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00000C00	1	0	not checked	not checked	0
#74W-destination-4	489	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00001000	1	0	not checked	not checked	0
#75W-destination-5	495	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00001400	1	0	not checked	not checked	0
#76W-destination-6	501	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00001800	1	0	not checked	not checked	0
#77W-destination-7	507	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00001C00	1	0	not checked	not checked	0
#78W-destination-8	512	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00002000	1	0	not checked	not checked	0
#79W-destination-9	518	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00002400	1	0	not checked	not checked	0
#80W-destination-10	524	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00002800	1	0	not checked	not checked	0
#81W-destination-11	530	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00002C00	1	0	not checked	not checked	0
#82W-destination-12	535	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00003000	1	0	not checked	not checked	0
#83W-destination-13	541	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00003400	1	0	not checked	not checked	0
#84W-destination-14	547	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00003800	1	0	not checked	not checked	0
#85W-destination-15	553	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00003C00	1	0	not checked	not checked	0
#86W-destination-16	559	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00004000	1	0	not checked	not checked	0
#87W-destination-17	566	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00004400	1	0	not checked	not checked	0
#88W-destination-18	573	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00004800	1	0	not checked	not checked	0
#89W-destination-19	580	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00004C00	1	0	not checked	not checked	0
#90W-destination-20	586	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00005000	1	0	not checked	not checked	0
#91W-destination-21	592	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00005400	1	0	not checked	not checked	0
#92W-destination-22	598	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00005800	1	0	not checked	not checked	0
#93W-destination-23	604	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00005C00	1	0	not checked	not checked	0
#94W-destination-24	609	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00006000	1	0	not checked	not checked	0
#95W-destination-25	615	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00006400	1	0	not checked	not checked	0
#96W-destination-26	621	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00006800	1	0	not checked	not checked	0
#97W-destination-27	627	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00006C00	1	0	not checked	not checked	0
#98W-destination-28	632	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00007000	1	0	not checked	not checked	0
#99W-destination-29	638	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00007400	1	0	not checked	not checked	0
#100W-destination-30	644	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00007800	1	0	not checked	not checked	0
#101W-destination-31	650	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00007C00	1	0	not checked	not checked	0
#102W-disabled-producer	660	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000000	0x00000400	1	0	not checked	not checked	not checked
#103W-bubble	663	0x00000180	0x00000041	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0	not checked	not checked	not checked
#104unused-encoded-source	667	0x00000000	0x00000041	1	0x00000002	0x00000400	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0	not checked	not checked	not checked
#105invalid-decode	671	0x00000080	0x00000041	0	0x00000002	0x00000400	1	0x00000002	0x00000400	0	0x00000002	0x00000400	0	0	not checked	not checked	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Open dependency unit

Tests

RV32IBaselineDependencyUnitTest compares both implementations. Dependent-ALU and load-use program cases verify the resulting stalls in the complete pipeline.

4.5.7.2. RV32IBaselineControl

IO pins

Pin	Direction	Width	Description
ENABLE, RST, HALTED, TRAPPED	Input	1 each	Global execution permission and state
DATA_HAZARD	Input	1	Decode needs an older register result
D_CONTROL_FLOW, E_CONTROL_FLOW	Input	1 each	Valid branch/jump in Decode or Execute
D_TERMINAL, E_TERMINAL, M_TERMINAL, W_TERMINAL	Input	1 each	Valid terminal reason at each stage
ACTIVE, COMMIT_ENABLE, MEMORY_ENABLE	Output	1 each	Global advance, WB commit, permitted native memory operation
FETCH_VALID, PC_WRITE, PC_REDIRECT	Output	1 each	Accept instruction; update fetch PC; use resolved PC
IF_ID_WRITE, ID_EX_WRITE, EX_MEM_WRITE, MEM_WB_WRITE	Output	1 each	Enable each pipeline register
IF_ID_FLUSH, ID_EX_FLUSH, EX_MEM_FLUSH, MEM_WB_FLUSH	Output	1 each	Capture bubble when that register is enabled
DATA_STALL, BRANCH_WAIT, PIPELINE_FLUSH	Output	1 each	Active-cycle diagnostic conditions

Behavior

A stall does not stop the clock

The controller drives the pipeline registers' WRITE_ENABLE and FLUSH pins. WRITE_ENABLE=0 holds the stored instruction. WRITE_ENABLE=1 captures the next packet; FLUSH=1 makes that captured packet invalid, creating a bubble. The payload bits need not be zero, but an invalid slot cannot write registers or memory or retire.

For a data dependency, CONTROL holds the fetch PC and IF/ID, inserts a bubble into ID/EX, and lets EX/MEM and MEM/WB advance. This keeps the waiting instruction in Decode while older instructions finish. Holding the whole pipeline would prevent the producer from writing the value the consumer needs.

The controller does not turn a clock off or run a software wait loop. In the structural implementation, combinational gates compute the enables and flushes from the current stage signals. All storage then reacts to the same rising edge.

Movement and priority

Situation	Fetch / IF-ID	ID-EX	Older stages
Normal	Accept and advance	Advance	Advance
RAW dependency	Hold	Bubble	Advance so producer can finish
Branch in Decode, operands ready	Stop fetch; clear younger slot	Accept branch	Advance
Branch in Execute	Resolve PC; do not accept old fetch	Bubble	Branch advances
Terminal instruction	Stop younger work	Bubble younger slots	Terminal and older instructions drain to WB
Disabled, reset, halted, trapped	No advancing writes	Hold except reset	No retirement or memory write

Terminal priority follows age. A terminal instruction in WB suppresses a younger MEM store. A MEM terminal instruction suppresses a younger Execute redirect. Reset also reaches the storage components directly; their asynchronous resets are not implemented by these flush outputs.

FLUSH outputs describe bubble conditions even while inactive; the corresponding WRITE outputs are zero, so storage holds. PIPELINE_FLUSH is a cycle-level condition, not a unique branch-event pulse. BRANCH_WAIT can overlap DATA_STALL when a branch waits for a register operand.

C++ example

This includes every control output and the priority rules, including impossible input combinations used by the exhaustive component test. Real integrated stage terminal/control-flow signals are validity-qualified.

struct ControlInputs {
    bool enable,reset,halted,trapped,data_hazard,d_control_flow,e_control_flow;
    bool d_terminal,e_terminal,m_terminal,w_terminal;
};
struct ControlOutputs {
    bool active,fetch_valid,pc_write,pc_redirect;
    bool if_id_write,if_id_flush,id_ex_write,id_ex_flush;
    bool ex_mem_write,ex_mem_flush,mem_wb_write,mem_wb_flush;
    bool memory_enable,commit_enable,data_stall,branch_wait,pipeline_flush;
};
inline ControlOutputs control(const ControlInputs& i) {
    const bool active=i.enable&&!i.reset&&!i.halted&&!i.trapped;
    const bool late=i.m_terminal||i.w_terminal,older=i.e_terminal||late;
    const bool terminal=older||(i.d_terminal&&!i.e_control_flow);
    const bool stall=i.data_hazard&&!i.d_terminal&&!older;
    const bool branch=i.d_control_flow||i.e_control_flow;
    const bool fetch=active&&!terminal&&!stall&&!branch;
    const bool redirect=active&&i.e_control_flow&&!older;
    return {active,fetch,fetch||redirect,redirect,
        active&&(!stall||i.e_control_flow),terminal||branch,active,stall||older||i.e_control_flow,
        active,late,active,i.w_terminal,
        active&&!i.w_terminal,active,active&&stall,active&&branch,active&&(terminal||branch)};
}

Implementation

Structural implementation

AND/OR/NOT gates form execution permission, dependency wait, branch resolution, age-prioritized terminal conditions, and stage enables. MEM_WB_FLUSH is W_TERMINAL wired straight through. The complete core keeps this logic in the CONTROL block below the datapath.

Behavioral implementation

control evaluates the same combinational Boolean equations. It has no clock or pending state. The family is rv32i.baseline.control.

Examples

The following walkthroughs describe active cycles after reset, with ENABLE=1, no faults, and no halt/trap. A cycle means the work before its ending rising edge; captures and writes occur at that edge. These cycle numbers explain the instruction sequence, not simulator timestamps or checkpoint numbers. The complete recorded test rows follow the walkthroughs.

Data hazard: hold the consumer, advance the producer

addi x1, x0, 5     # A: produces x1
add  x2, x1, x1    # B: consumes x1

Start with an empty pipeline. In cycle 3, A is in Execute and B is in Decode. DEPENDENCIES sees that B reads the register A will write and raises DATA_HAZARD.

At that cycle's ending edge:

1. PC_WRITE=0 holds the fetch PC; FETCH_VALID=0 accepts no new fetched instruction.
2. IF_ID_WRITE=0 keeps B in IF/ID, so Decode continues to see B.
3. ID_EX_WRITE=1 and ID_EX_FLUSH=1 put a bubble into Execute instead of B's not-yet-ready operands.
4. EX_MEM_WRITE=1 and MEM_WB_WRITE=1 let older instructions advance. Their flush inputs remain zero; A moves into Memory.

Cycle	A	B	Dependency / ending-edge action
1	Fetch	Not fetched	IF/ID captures A
2	Decode	Fetch	ID/EX captures A; IF/ID captures B
3	Execute	Decode, waiting	WAIT_EX=1; hold B and insert a bubble into ID/EX
4	Memory	Decode, waiting	WAIT_MEM=1; hold B and insert another bubble
5	Writeback	Decode, waiting	WAIT_WB=1; A writes x1=5 at the ending edge; B still does not advance on that edge
6	Finished	Decode, ready	DATA_HAZARD=0; B reads the updated x1 and captures both operands into ID/EX
7	Finished	Execute	B computes 5+5
8	Finished	Memory	B carries its arithmetic result through Memory
9	Finished	Writeback	B writes x2=10

The important distinction is that B waits, but A keeps moving. There is no forwarding path and no same-edge Writeback-to-Decode bypass. Stores and branches also wait if their actually used source registers depend on an older writer.

Jump: stop younger fetches, let the jump resolve

jal  x0, target    # PC=0: jump to PC=8; discard the link value
addi x1, x0, 99    # PC=4: skipped
target:
addi x2, x0, 7     # PC=8: target instruction

This example also starts with an empty pipeline. The jump has no source-register dependency.

Cycle	Jump's stage	Fetch and ending-edge action
1	Fetch	Accept the jump into IF/ID and advance the fetch PC to 4
2	Decode	D_CONTROL_FLOW=1 stops fetch acceptance. ID/EX captures the jump; IF/ID captures a bubble. The fetch PC stays 4
3	Execute	EXECUTE selects address 8. PC_REDIRECT=1 and PC_WRITE=1 load 8 into the fetch-PC register; younger slots remain bubbles
4	Memory	Fetch accepts the target instruction at address 8
5	Writeback	The jump retires; the target instruction is already in Decode

In cycle 2, IF_ID_WRITE=1 and IF_ID_FLUSH=1 clear the old Decode slot, while ID_EX_WRITE=1 and ID_EX_FLUSH=0 transfer the jump into Execute. All registers capture from pre-edge signals, so the jump is copied forward before the changed IF/ID outputs propagate; it is not lost or executed twice.

In cycle 3, FETCH_VALID remains zero. The redirect updates the PC at the edge; target fetching starts in cycle 4, not during the resolution cycle. The instruction at address 4 may appear on the memory wires, but it is never accepted as a valid younger instruction.

Conditional branches use the same wait: Execute selects the target if taken, or PC+4 if untaken. An untaken branch still incurs the wait. JALR also resolves in Execute, using its captured source operand. A JAL/JALR with a nonzero destination writes its link value later in Writeback; Fetch does not wait for that retirement.

A branch or JALR can wait for data too

For addi x1,x0,8 followed by jalr x0,0(x1), both DATA_HAZARD and D_CONTROL_FLOW are initially one while JALR is in Decode. The controller keeps IF_ID_WRITE=0, even though IF_ID_FLUSH=1. A flush does not override a hold, so the waiting JALR remains in IF/ID rather than disappearing.

Once x1 has been written and DATA_HAZARD clears, the controller transfers JALR into Execute and bubbles IF/ID. Execute then resolves address 8; Fetch resumes afterward. BRANCH_WAIT can therefore overlap DATA_STALL: they are conditions, not counts that should simply be added together.

Signals behind the walkthroughs

These are the named checkpoints in the component simulation below. WRITE / FLUSH describes what the corresponding pipeline register does at an edge; EX/MEM and MEM/WB advance without flushing in all five rows.

Checkpoint	FETCH_VALID	PC_WRITE	PC_REDIRECT	IF_ID WRITE / FLUSH	ID_EX WRITE / FLUSH
normal-flow	1	1	0	1 / 0: advance	1 / 0: advance
raw-wait	0	0	0	0 / 0: hold consumer	1 / 1: bubble
branch-waits-for-operand	0	0	0	0 / 1: hold branch	1 / 1: bubble
branch-enters-execute	0	0	0	1 / 1: bubble	1 / 0: accept branch
branch-resolves	0	1	1	1 / 1: bubble	1 / 1: bubble

RV32IBaselineDocumentationTest checks this signal summary against the simulator's exported checkpoint values. The walkthroughs describe normal operation; the full behavior and C++ example above also cover older faults, reset, and disabled execution.

Complete checkpoint table

The first rows name common transitions. The remaining rows enumerate all 2,048 binary combinations of the eleven inputs; the scrollable table includes every row and checkpoint time. To inspect the decisions above, use raw-wait, branch-waits-for-operand, branch-enters-execute, and branch-resolves before the exhaustive rows.

All 2058 recorded rows of RV32IBaselineControlTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: baseline-structural-stages / structural (f72af366c5dca6eb). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	DATA_HAZARDInput · 1 bit	D_CONTROL_FLOWInput · 1 bit	D_TERMINALInput · 1 bit	ENABLEInput · 1 bit	E_CONTROL_FLOWInput · 1 bit	E_TERMINALInput · 1 bit	HALTEDInput · 1 bit	M_TERMINALInput · 1 bit	RSTInput · 1 bit	TRAPPEDInput · 1 bit	W_TERMINALInput · 1 bit	ACTIVEExpected output · 1 bit	BRANCH_WAITExpected output · 1 bit	COMMIT_ENABLEExpected output · 1 bit	DATA_STALLExpected output · 1 bit	EX_MEM_FLUSHExpected output · 1 bit	EX_MEM_WRITEExpected output · 1 bit	FETCH_VALIDExpected output · 1 bit	ID_EX_FLUSHExpected output · 1 bit	ID_EX_WRITEExpected output · 1 bit	IF_ID_FLUSHExpected output · 1 bit	IF_ID_WRITEExpected output · 1 bit	MEMORY_ENABLEExpected output · 1 bit	MEM_WB_FLUSHExpected output · 1 bit	MEM_WB_WRITEExpected output · 1 bit	PC_REDIRECTExpected output · 1 bit	PC_WRITEExpected output · 1 bit	PIPELINE_FLUSHExpected output · 1 bit
#0initial-inputs	5	0	0	0	0	0	0	0	0	1	0	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#1normal-flow	12	0	0	0	1	0	0	0	0	0	0	0	not checked	not checked	not checked	not checked	not checked	not checked	1	0	not checked	not checked	1	1	not checked	not checked	not checked	1	not checked
#2raw-wait	19	1	0	0	1	0	0	0	0	0	0	0	not checked	not checked	not checked	not checked	0	not checked	0	1	1	not checked	0	not checked	not checked	not checked	not checked	not checked	not checked
#3branch-waits-for-operand	23	1	1	0	1	0	0	0	0	0	0	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	1	0	not checked	not checked	not checked	0	not checked	not checked
#4branch-enters-execute	29	0	1	0	1	0	0	0	0	0	0	0	not checked	not checked	not checked	not checked	not checked	not checked	0	0	not checked	1	1	not checked	not checked	not checked	not checked	not checked	not checked
#5branch-resolves	33	0	0	0	1	1	0	0	0	0	0	0	not checked	not checked	not checked	not checked	not checked	not checked	0	1	not checked	not checked	not checked	not checked	not checked	not checked	1	1	not checked
#6older-memory-fault-wins	40	0	0	0	1	1	0	0	1	0	0	0	not checked	not checked	not checked	not checked	1	not checked	not checked	not checked	not checked	not checked	not checked	not checked	0	not checked	0	not checked	not checked
#7oldest-terminal-blocks-store	43	0	0	0	1	1	0	0	1	0	0	1	not checked	not checked	1	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	0	1	not checked	not checked	not checked	not checked
#8disabled-holds	48	0	0	0	0	1	0	0	1	0	0	1	0	not checked	0	not checked	not checked	0	not checked	not checked	0	not checked	0	not checked	not checked	0	not checked	not checked	not checked
#9reset	54	0	0	0	1	1	0	0	1	1	0	1	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	0	not checked	not checked	not checked	not checked	not checked
#10control-inputs-0	60	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#11control-inputs-1	66	0	0	0	1	0	0	0	0	0	0	0	1	0	1	0	0	1	1	0	1	0	1	1	0	1	0	1	0
#12control-inputs-2	72	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#13control-inputs-3	74	0	0	0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#14control-inputs-4	78	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#15control-inputs-5	81	0	0	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#16control-inputs-6	84	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#17control-inputs-7	86	0	0	0	1	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#18control-inputs-8	89	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#19control-inputs-9	92	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#20control-inputs-10	95	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#21control-inputs-11	97	0	0	0	1	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#22control-inputs-12	100	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#23control-inputs-13	103	0	0	0	1	0	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#24control-inputs-14	106	0	0	0	0	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#25control-inputs-15	108	0	0	0	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#26control-inputs-16	114	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#27control-inputs-17	119	1	0	0	1	0	0	0	0	0	0	0	1	0	1	1	0	1	0	1	1	0	0	1	0	1	0	0	0
#28control-inputs-18	124	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#29control-inputs-19	126	1	0	0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#30control-inputs-20	130	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#31control-inputs-21	133	1	0	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#32control-inputs-22	136	1	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#33control-inputs-23	138	1	0	0	1	0	0	1	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#34control-inputs-24	141	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#35control-inputs-25	144	1	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#36control-inputs-26	147	1	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#37control-inputs-27	149	1	0	0	1	0	0	0	0	1	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#38control-inputs-28	152	1	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#39control-inputs-29	155	1	0	0	1	0	0	1	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#40control-inputs-30	158	1	0	0	0	0	0	1	0	1	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#41control-inputs-31	160	1	0	0	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
#42control-inputs-32	166	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#43control-inputs-33	171	0	1	0	1	0	0	0	0	0	0	0	1	1	1	0	0	1	0	0	1	1	1	1	0	1	0	0	1
#44control-inputs-34	176	0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#45control-inputs-35	178	0	1	0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#46control-inputs-36	182	0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#47control-inputs-37	185	0	1	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#48control-inputs-38	188	0	1	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#49control-inputs-39	190	0	1	0	1	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#50control-inputs-40	193	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#51control-inputs-41	196	0	1	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#52control-inputs-42	199	0	1	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#53control-inputs-43	201	0	1	0	1	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#54control-inputs-44	204	0	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#55control-inputs-45	207	0	1	0	1	0	0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#56control-inputs-46	210	0	1	0	0	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
#57control-inputs-47	212	0	1	0	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
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#1950control-inputs-1940	6071	1	0	1	0	0	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1951control-inputs-1941	6074	1	0	1	1	0	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1952control-inputs-1942	6077	1	0	1	0	0	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1953control-inputs-1943	6079	1	0	1	1	0	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1954control-inputs-1944	6082	1	0	1	0	0	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1955control-inputs-1945	6085	1	0	1	1	0	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1956control-inputs-1946	6088	1	0	1	0	0	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1957control-inputs-1947	6090	1	0	1	1	0	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1958control-inputs-1948	6093	1	0	1	0	0	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1959control-inputs-1949	6096	1	0	1	1	0	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1960control-inputs-1950	6099	1	0	1	0	0	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1961control-inputs-1951	6101	1	0	1	1	0	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1962control-inputs-1952	6106	0	1	1	0	0	1	0	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1963control-inputs-1953	6110	0	1	1	1	0	1	0	1	0	0	1	1	1	1	0	1	1	0	1	1	1	1	0	1	1	0	0	1
#1964control-inputs-1954	6114	0	1	1	0	0	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1965control-inputs-1955	6116	0	1	1	1	0	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1966control-inputs-1956	6120	0	1	1	0	0	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1967control-inputs-1957	6123	0	1	1	1	0	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1968control-inputs-1958	6126	0	1	1	0	0	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1969control-inputs-1959	6128	0	1	1	1	0	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1970control-inputs-1960	6131	0	1	1	0	0	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1971control-inputs-1961	6134	0	1	1	1	0	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1972control-inputs-1962	6137	0	1	1	0	0	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1973control-inputs-1963	6139	0	1	1	1	0	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1974control-inputs-1964	6142	0	1	1	0	0	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1975control-inputs-1965	6145	0	1	1	1	0	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1976control-inputs-1966	6148	0	1	1	0	0	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1977control-inputs-1967	6150	0	1	1	1	0	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1978control-inputs-1968	6154	1	1	1	0	0	1	0	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1979control-inputs-1969	6158	1	1	1	1	0	1	0	1	0	0	1	1	1	1	0	1	1	0	1	1	1	1	0	1	1	0	0	1
#1980control-inputs-1970	6162	1	1	1	0	0	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1981control-inputs-1971	6164	1	1	1	1	0	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1982control-inputs-1972	6168	1	1	1	0	0	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1983control-inputs-1973	6171	1	1	1	1	0	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1984control-inputs-1974	6174	1	1	1	0	0	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1985control-inputs-1975	6176	1	1	1	1	0	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1986control-inputs-1976	6179	1	1	1	0	0	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1987control-inputs-1977	6182	1	1	1	1	0	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1988control-inputs-1978	6185	1	1	1	0	0	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1989control-inputs-1979	6187	1	1	1	1	0	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1990control-inputs-1980	6190	1	1	1	0	0	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1991control-inputs-1981	6193	1	1	1	1	0	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1992control-inputs-1982	6196	1	1	1	0	0	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1993control-inputs-1983	6198	1	1	1	1	0	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1994control-inputs-1984	6202	0	0	1	0	1	1	0	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1995control-inputs-1985	6207	0	0	1	1	1	1	0	1	0	0	1	1	1	1	0	1	1	0	1	1	1	1	0	1	1	0	0	1
#1996control-inputs-1986	6212	0	0	1	0	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1997control-inputs-1987	6214	0	0	1	1	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1998control-inputs-1988	6218	0	0	1	0	1	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#1999control-inputs-1989	6221	0	0	1	1	1	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2000control-inputs-1990	6224	0	0	1	0	1	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2001control-inputs-1991	6226	0	0	1	1	1	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2002control-inputs-1992	6229	0	0	1	0	1	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2003control-inputs-1993	6232	0	0	1	1	1	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2004control-inputs-1994	6235	0	0	1	0	1	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2005control-inputs-1995	6237	0	0	1	1	1	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2006control-inputs-1996	6240	0	0	1	0	1	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2007control-inputs-1997	6243	0	0	1	1	1	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2008control-inputs-1998	6246	0	0	1	0	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2009control-inputs-1999	6248	0	0	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2010control-inputs-2000	6252	1	0	1	0	1	1	0	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2011control-inputs-2001	6257	1	0	1	1	1	1	0	1	0	0	1	1	1	1	0	1	1	0	1	1	1	1	0	1	1	0	0	1
#2012control-inputs-2002	6262	1	0	1	0	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2013control-inputs-2003	6264	1	0	1	1	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2014control-inputs-2004	6268	1	0	1	0	1	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2015control-inputs-2005	6271	1	0	1	1	1	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2016control-inputs-2006	6274	1	0	1	0	1	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2017control-inputs-2007	6276	1	0	1	1	1	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2018control-inputs-2008	6279	1	0	1	0	1	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2019control-inputs-2009	6282	1	0	1	1	1	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2020control-inputs-2010	6285	1	0	1	0	1	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
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#2022control-inputs-2012	6290	1	0	1	0	1	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2023control-inputs-2013	6293	1	0	1	1	1	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2024control-inputs-2014	6296	1	0	1	0	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2025control-inputs-2015	6298	1	0	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2026control-inputs-2016	6302	0	1	1	0	1	1	0	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2027control-inputs-2017	6307	0	1	1	1	1	1	0	1	0	0	1	1	1	1	0	1	1	0	1	1	1	1	0	1	1	0	0	1
#2028control-inputs-2018	6312	0	1	1	0	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
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#2040control-inputs-2030	6346	0	1	1	0	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2041control-inputs-2031	6348	0	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
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#2043control-inputs-2033	6357	1	1	1	1	1	1	0	1	0	0	1	1	1	1	0	1	1	0	1	1	1	1	0	1	1	0	0	1
#2044control-inputs-2034	6362	1	1	1	0	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2045control-inputs-2035	6364	1	1	1	1	1	1	0	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2046control-inputs-2036	6368	1	1	1	0	1	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2047control-inputs-2037	6371	1	1	1	1	1	1	1	1	0	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2048control-inputs-2038	6374	1	1	1	0	1	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2049control-inputs-2039	6376	1	1	1	1	1	1	1	1	1	0	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2050control-inputs-2040	6379	1	1	1	0	1	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2051control-inputs-2041	6382	1	1	1	1	1	1	0	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2052control-inputs-2042	6385	1	1	1	0	1	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2053control-inputs-2043	6387	1	1	1	1	1	1	0	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2054control-inputs-2044	6390	1	1	1	0	1	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2055control-inputs-2045	6393	1	1	1	1	1	1	1	1	0	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2056control-inputs-2046	6396	1	1	1	0	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0
#2057control-inputs-2047	6398	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	0	1	0	1	0	0	1	0	0	0	0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Open pipeline control

Tests

RV32IBaselineControlTest checks the complete binary truth table and structural/behavioral equivalence. Connected-core tests check that the enables actually hold/bubble the intended pipeline registers. Sources: RV32IBaselinePipeline.cpp, RV32IBaselinePipelineBehavioral.cpp.

Shared structural helper: RV32IBaselinePacketStatus

Decode, Execute, and Memory contain a PACKET_STATUS child. This is a grouping of existing Boolean gates and field rewiring, not a new stage or storage element. It keeps the main datapath visible without a row of small status gates dominating each stage view.

Its inputs are VALID (1 bit) and CONTROL, FETCH_STATUS, EXECUTION_STATUS (32 bits each); its outputs are TERMINAL and CONTROL_FLOW (1 bit each). Only the defined status/control bits matter. Decode supplies zero EXECUTION_STATUS; Execute supplies its newly calculated status; Memory supplies the captured EX/MEM status.

bool terminal = valid && ((fetch_status & 3) || !(control & 1) ||
                          (control & ((1u << 5) | (1u << 6))) ||
                          (execution_status & 1));
bool control_flow = valid && (((control >> 13) & 7) || ((control >> 16) & 3));

The helper is internal, with no independent fidelity selector or behavioral variant. Its equations are included in each enclosing stage's behavioral implementation and verified through those stages' equivalence tests. Inspect PACKET_STATUS inside any of the three embedded stage simulations to see the structural gates.