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ยง 4.5.8. Complete Core

RV32IBaselinePipelineCore is the zero-wait-memory, stall-only RV32I pipeline. It retains the same instruction semantics and machine contract as the single-cycle implementation. Instructions overlap, but execute and retire in order.

Component Description Structural Behavioral
RV32IBaselinePipelineCore Five stages, four pipeline registers, dependency and control blocks Yes Yes

IO pins

Pin Direction Width Description
CLK, RST, ENABLE Input 1 each Rising-edge state advance, asynchronous reset, global execution enable
IMEM_REQ_READY, DMEM_REQ_READY Input 1 each Endpoint can accept the request on the next edge
IMEM_RSP_VALID, DMEM_RSP_VALID Input 1 each Endpoint response is present during this cycle
IMEM_RSP_READ_DATA, DMEM_RSP_READ_DATA Input 32 each Instruction/data response
IMEM_RSP_STATUS, DMEM_RSP_STATUS Input 3 each Zero success; nonzero access error
IMEM_REQ_ADDR, DMEM_REQ_ADDR Output 32 each Aligned byte addresses
IMEM_REQ_OP, DMEM_REQ_OP Output 3 each READ=0; data WRITE=1
IMEM_REQ_VALID, DMEM_REQ_VALID Output 1 each Active access
IMEM_REQ_WRITE_DATA, DMEM_REQ_WRITE_DATA Output 32 each Positioned store data; instruction port zero
IMEM_REQ_WRITE_MASK, DMEM_REQ_WRITE_MASK Output 4 each Store byte enables; instruction port zero
IMEM_RSP_READY, DMEM_RSP_READY Output 1 each Always accept a response
FETCH_PC Output 32 Current fetch PC; completed PC is host-side observation, not a core pin
HALTED, TRAPPED, TRAP_CAUSE Output 1, 1, 4 Architectural stopping state
INSTRUCTION_ATTEMPT, COMMIT_VALID Output 1 each Accept current fetch packet; permit current WB retirement
IF_ID_VALID, ID_EX_VALID, EX_MEM_VALID, MEM_WB_VALID Output 1 each Occupied instruction slots
IF_ID_PC, ID_EX_PC, EX_MEM_PC, MEM_WB_PC Output 32 each Stored slot PC; meaningful as an instruction only when valid
DATA_STALL, PIPELINE_STALL Output 1 each Same active RAW-stall condition
BRANCH_WAIT, PIPELINE_FLUSH Output 1 each Branch waiting; active younger-slot bubble condition
LOAD_USE_STALL, MEMORY_STALL, DATA_PORT_STALL Output 1 each Compatibility observations, always zero in this baseline

The pin names are universal, but the baseline timing contract requires a response in the request cycle. Default FF endpoints satisfy it. Delayed endpoints require the transaction-capable pipeline; these pins alone do not add stall control.

Behavior

The stage contracts define data transformation. Control decides whether each packet advances. All stages use pre-edge state; all enabled registers then capture together. Execute never re-reads a register updated by that same instruction. There is no combinational route around a pipeline register or hidden functional instruction execution in the structural core.

An independent stream first retires on the fifth active edge and can then retire one instruction per cycle. An immediate RAW consumer waits through the producer's EX, MEM, and WB stages. Branches wait for Execute whether taken or untaken. These are performance differences, not changes to instruction semantics.

ENABLE=0 freezes PC, pipeline registers, register-file updates and retirement, and suppresses stores. Reset clears architectural state and pipeline validity; externally provisioned memory images remain intact. Only valid instructions can retire or write memory. Older faults suppress younger stores and redirects; fault information travels with the instruction until WB.

Binary example types

The complete example header provides the C++ examples used throughout 4.5. It is ordinary binary C++ with no simulator events; it reuses the already documented instruction decoder and encoded control definitions. Packet members correspond to the named fields in 4.5.1; only the fields present at that boundary are stored.

struct Packet {
    bool valid=false;
    uint32_t pc=0, instruction=0, fetch_status=0;
    uint32_t rs1_value=0, rs2_value=0, immediate=0;
    uint32_t control=0, addresses=0;
    uint32_t alu_result=0, store_data=0, pc_plus_4=0, next_pc=0;
    uint32_t execution_status=0, memory_data=0, memory_status=0;
};
struct StageResult { Packet packet; bool terminal, control_flow; };

The one-edge ordering is: evaluate Decode/Execute/Memory and control from the old packets and register file; evaluate retiring WB; then capture each enabled pipeline register. A WB register write must not alter the already computed Decode packet on that same edge. In the structural simulator, the pipeline-register edges enforce this naturally. The compact model computes all candidate packets before changing its stored state.

Implementation

Structural implementation

Child Responsibility
FETCH, IF_ID, DECODE, ID_EX, EXECUTE, EX_MEM, MEMORY, MEM_WB, WRITEBACK Left-to-right pipeline datapath, alternating stages and packet registers
DEPENDENCIES Three older-producer comparisons
CONTROL Stage enables, bubbles, branch wait, precise stopping
EXECUTION_STATUS Sticky halt/trap flags and four-bit cause; six storage bits outside Writeback
INSTRUCTION_PORT, DATA_PORT Combinational stage-to-transaction formatting, without state or wait cycles
NO_MEMORY_WAIT Constant zero for compatibility diagnostic outputs

The floorplan preserves stage order even though control and register-write feedback wires run backward. There are no stateful memory requesters, cache controllers, instruction/data arrays, or forwarding units hidden in the core. Port-formatting groups translate stage-local word addresses to byte-addressed transactions.

Behavioral implementation

BehavioralCore stores four instruction packets, the fetch PC, register values, and halt/trap status. It evaluates the same cycle rules independently of the structural wiring. It does not run an architectural oracle internally and does not instantiate a shadow structural CPU. Both forms share rv32i.core.baseline-pipeline, a pipeline-state view accepting a host-observed PC and a read-only view of the pending MEM/WB retirement packet. Neither keeps retirement counters or saved trace records.

Examples

This connected-core scenario fills all four pipeline registers with independent instructions, pauses while they are occupied, resumes, drains a halt, and resets. Each expected row is checked in both fidelities.

All 28 recorded rows of RV32IBaselinePipelineCoreTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: baseline-structural-stages / structural (f72af366c5dca6eb). Changing fidelity or the circuit can change these times.

Checkpointzero-based number ยท timeline label Timesimulator units CLKInput ยท 1 bit DMEM_REQ_READYInput ยท 1 bit DMEM_RSP_READ_DATAInput ยท 32 bit DMEM_RSP_STATUSInput ยท 3 bit DMEM_RSP_VALIDInput ยท 1 bit ENABLEInput ยท 1 bit IMEM_REQ_READYInput ยท 1 bit IMEM_RSP_READ_DATAInput ยท 32 bit IMEM_RSP_STATUSInput ยท 3 bit IMEM_RSP_VALIDInput ยท 1 bit RSTInput ยท 1 bit BRANCH_WAITExpected output ยท 1 bit COMMIT_VALIDExpected output ยท 1 bit DATA_PORT_STALLExpected output ยท 1 bit DATA_STALLExpected output ยท 1 bit DMEM_REQ_ADDRExpected output ยท 32 bit DMEM_REQ_OPExpected output ยท 3 bit DMEM_REQ_VALIDExpected output ยท 1 bit DMEM_REQ_WRITE_DATAExpected output ยท 32 bit DMEM_REQ_WRITE_MASKExpected output ยท 4 bit DMEM_RSP_READYExpected output ยท 1 bit EX_MEM_PCExpected output ยท 32 bit EX_MEM_VALIDExpected output ยท 1 bit FETCH_PCExpected output ยท 32 bit HALTEDExpected output ยท 1 bit ID_EX_PCExpected output ยท 32 bit ID_EX_VALIDExpected output ยท 1 bit IF_ID_PCExpected output ยท 32 bit IF_ID_VALIDExpected output ยท 1 bit IMEM_REQ_ADDRExpected output ยท 32 bit IMEM_REQ_OPExpected output ยท 3 bit IMEM_REQ_VALIDExpected output ยท 1 bit IMEM_REQ_WRITE_DATAExpected output ยท 32 bit IMEM_REQ_WRITE_MASKExpected output ยท 4 bit IMEM_RSP_READYExpected output ยท 1 bit INSTRUCTION_ATTEMPTExpected output ยท 1 bit LOAD_USE_STALLExpected output ยท 1 bit MEMORY_STALLExpected output ยท 1 bit MEM_WB_PCExpected output ยท 32 bit MEM_WB_VALIDExpected output ยท 1 bit PIPELINE_FLUSHExpected output ยท 1 bit PIPELINE_STALLExpected output ยท 1 bit TRAPPEDExpected output ยท 1 bit TRAP_CAUSEExpected output ยท 4 bit
#0initial-inputs37 0 0 0x00000000 0x0 0 0 0 0x00000000 0x0 0 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#1release-reset45 0 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#2clock-low-146 0 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#3fill-174 1 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked 0 not checked 0 not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked 0 not checked 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked
#4clock-low-275 0 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#5fill-298 1 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked 0 not checked 0 not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked 1 not checked 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked
#6clock-low-399 0 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#7fill-3122 1 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked 0 not checked 0 not checked not checked not checked not checked not checked not checked not checked 1 not checked not checked not checked 1 not checked 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked
#8clock-low-4123 0 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#9fill-4145 1 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked 1 not checked 0 not checked not checked not checked not checked not checked not checked not checked 1 not checked not checked not checked 1 not checked 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 1 not checked not checked not checked not checked
#10clock-low-5146 0 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#11fill-5169 1 1 0x00000000 0x0 1 1 1 0x00100093 0x0 1 0 not checked 1 not checked 0 not checked not checked not checked not checked not checked not checked not checked 1 not checked not checked not checked 1 not checked 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 1 not checked not checked not checked not checked
#12pause185 0 1 0x00000000 0x0 1 0 1 0x00100093 0x0 1 0 not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#13paused-edge201 1 1 0x00000000 0x0 1 0 1 0x00100093 0x0 1 0 not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked 0x00000008 not checked 0x00000014 not checked 0x0000000C not checked 0x00000010 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0x00000004 not checked not checked not checked not checked not checked
#14resume-with-halt208 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#15clock-low-6209 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#16drain-6232 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked
#17clock-low-7233 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#18drain-7256 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked
#19clock-low-8257 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#20drain-8279 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked
#21clock-low-9280 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#22drain-9297 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked
#23clock-low-10298 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#24drain-10314 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 1 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked
#25post-halt-low315 0 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#26halted-holds331 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 0 not checked 0 not checked not checked not checked not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked
#27reset-flushes350 1 1 0x00000000 0x0 1 1 1 0x00100073 0x0 1 1 not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 0x00000000 not checked not checked 0 not checked 0 not checked not checked not checked not checked not checked not checked not checked not checked not checked not checked 0 not checked not checked not checked not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Open baseline core

Memory integration

Program fixtures supply separate MemoryEndpoint<ff,32> instances for instructions and data, each 65,536 words (256 KiB) by default. Both ports require zero-wait timing: instruction/data reads and response status settle within the current cycle, and authorized stores use the shared rising edge. Fetch captures the instruction into IF/ID and Memory forwards a load into MEM/WB without an extra memory-wait cycle.

Memory component or assembly Suitable for this core? Use
MemoryEndpoint<ff,32>, fused behavioral implementation Yes; default Scalable instruction and read/write data storage
MemoryEndpoint<ff,32>, visible FF controller plus native device Yes Same timing, with the controller/device boundary visible
MemoryEndpoint<sram,32>, <dram,32>, <rom,32>, <nor-flash,32> No, with their current controllers These endpoints require delayed-response handling
Native MemoryContainer, FFMemory, or other memory device alone Not directly Native pins need the matching controller to form an endpoint

The visible FF assembly can use MemoryContainer<ff,32> for scalable storage, or FFMemory<32> for a small cell-expanded circuit. Program-sized images should keep scalable storage. Capacity and fidelity do not change the timing contract. CPU reset clears the endpoint interface, not the stored program/data.

Hazard stalls are not memory-wait support

The baseline waits for register dependencies and branches, but does not hold its packets in response to REQ_READY=0 or RSP_VALID=0. Its memory-stall observation pins are always zero. The program root rejects non-FF configurations. Bypassing that guard with custom wiring can capture stale instructions/load values or lose stores; the result is not simply a slower pipeline. Delayed endpoints require the transaction-capable RV32IFiveStageCore, whose request tracking and pipeline control wait for completion.

Complete programs

All 22 programs from 4.2.3 are registered as RV32IBaselinePipelineProgramTest/program-01 through program-22. Their assembly, initial memory, expected instructions, and explanations are unchanged. Select rv32i-baseline-program1 through rv32i-baseline-program22 in the simulator.

The example below sums an array, branches around the loop, and stores its result. It uses two external zero-wait FF endpoints. Inspect CORE to see the baseline circuitry and use the instruction checkpoints to follow retirement.

All 29 instruction-attempt checkpoints of RV32IBaselinePipelineProgramTest/program-01, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

CheckpointTimeInstruction / addressExpected architectural effects
I024000ADDI @ 0x00000000raw=0x10000093, pc_after=0x00000004, wb=x1=0x00000100, mem=None, flow=next
I128000ADDI @ 0x00000004raw=0x00400113, pc_after=0x00000008, wb=x2=0x00000004, mem=None, flow=next
I232000ADDI @ 0x00000008raw=0x00000193, pc_after=0x0000000c, wb=x3=0x00000000, mem=None, flow=next
I340000LW @ 0x0000000craw=0x0000a203, pc_after=0x00000010, wb=x4=0x00000003, mem=Read Word @0x00000100 -> 0x00000003, flow=next
I456000ADD @ 0x00000010raw=0x004181b3, pc_after=0x00000014, wb=x3=0x00000003, mem=None, flow=next
I560000ADDI @ 0x00000014raw=0x00408093, pc_after=0x00000018, wb=x1=0x00000104, mem=None, flow=next
I664000ADDI @ 0x00000018raw=0xfff10113, pc_after=0x0000001c, wb=x2=0x00000003, mem=None, flow=next
I780000BNE @ 0x0000001craw=0xfe0118e3, pc_after=0x0000000c, wb=None, mem=None, branch=BNE taken=true
I892000LW @ 0x0000000craw=0x0000a203, pc_after=0x00000010, wb=x4=0x00000005, mem=Read Word @0x00000104 -> 0x00000005, flow=next
I9108000ADD @ 0x00000010raw=0x004181b3, pc_after=0x00000014, wb=x3=0x00000008, mem=None, flow=next
I10112000ADDI @ 0x00000014raw=0x00408093, pc_after=0x00000018, wb=x1=0x00000108, mem=None, flow=next
I11116000ADDI @ 0x00000018raw=0xfff10113, pc_after=0x0000001c, wb=x2=0x00000002, mem=None, flow=next
I12132000BNE @ 0x0000001craw=0xfe0118e3, pc_after=0x0000000c, wb=None, mem=None, branch=BNE taken=true
I13144000LW @ 0x0000000craw=0x0000a203, pc_after=0x00000010, wb=x4=0x00000007, mem=Read Word @0x00000108 -> 0x00000007, flow=next
I14160000ADD @ 0x00000010raw=0x004181b3, pc_after=0x00000014, wb=x3=0x0000000f, mem=None, flow=next
I15164000ADDI @ 0x00000014raw=0x00408093, pc_after=0x00000018, wb=x1=0x0000010c, mem=None, flow=next
I16168000ADDI @ 0x00000018raw=0xfff10113, pc_after=0x0000001c, wb=x2=0x00000001, mem=None, flow=next
I17184000BNE @ 0x0000001craw=0xfe0118e3, pc_after=0x0000000c, wb=None, mem=None, branch=BNE taken=true
I18196000LW @ 0x0000000craw=0x0000a203, pc_after=0x00000010, wb=x4=0x0000000b, mem=Read Word @0x0000010c -> 0x0000000b, flow=next
I19212000ADD @ 0x00000010raw=0x004181b3, pc_after=0x00000014, wb=x3=0x0000001a, mem=None, flow=next
I20216000ADDI @ 0x00000014raw=0x00408093, pc_after=0x00000018, wb=x1=0x00000110, mem=None, flow=next
I21220000ADDI @ 0x00000018raw=0xfff10113, pc_after=0x0000001c, wb=x2=0x00000000, mem=None, flow=next
I22236000BNE @ 0x0000001craw=0xfe0118e3, pc_after=0x00000020, wb=None, mem=None, branch=BNE taken=false
I23248000ADDI @ 0x00000020raw=0x12000293, pc_after=0x00000024, wb=x5=0x00000120, mem=None, flow=next
I24264000SW @ 0x00000024raw=0x0032a023, pc_after=0x00000028, wb=None, mem=Write Word @0x00000120 <- 0x0000001a, flow=next
I25268000SB @ 0x00000028raw=0x00328223, pc_after=0x0000002c, wb=None, mem=Write Byte @0x00000124 <- 0x0000001a, flow=next
I26272000ADDI @ 0x0000002craw=0x03418313, pc_after=0x00000030, wb=x6=0x0000004e, mem=None, flow=next
I27288000SH @ 0x00000030raw=0x00629323, pc_after=0x00000034, wb=None, mem=Write Halfword @0x00000126 <- 0x0000004e, flow=next
I28292000EBREAK @ 0x00000034raw=0x00100073, pc_after=0x00000034, wb=None, mem=None, flow=next, halted=true

Open array-sum program

Tests

RV32IBaselinePipelineCoreTest runs the connected-core scenario and all 22 programs. Each program compares architectural state and retired memory effects with the instruction oracle, checks physical memory writes independently, and compares structural/behavioral retirement times, cycle counts, RAW stalls, and branch-wait counts. The harness samples COMMIT_VALID and the MEM/WB packet before each edge, tracks completed PC and counts in host memory, and checks hardware state after the edge. The testbench PC output is this host observation, not a core register or feedback signal. This observation does not add circuitry to Writeback. Focused stage/control tests cover the smaller contracts.

These tests establish the baseline's simulated behavior. They do not establish realistic cache/DRAM latency, hardware clock frequency, or performance relative to a physical processor. Variable-latency memories and forwarding are outside this baseline; the existing advanced RV32IFiveStageCore supports them and shares the same simplified Writeback stage.

Sources: RV32IBaselinePipelineCore.cpp, RV32IBaselinePipelineBehavioral.cpp, RV32IBaselinePipelineTests.cpp, and the shared RV32I program tests.