Program 14: Out-of-range word store

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Purpose

Reject an aligned store beyond data memory without changing any bytes.

This is a negative test: the named trap is the expected outcome, not a failed simulation.

Setup

Property	Value
Benchmark workload ID	program-14
Headless selection	--program 14
Visualizer scenario	rv32i-program14
Registered test	RV32ISingleCycleSystemTest/program-14
Instruction image	4 words, starting at 0x00000000; last word at 0x0000000C
Initial state	PC = 0x00000000; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
x1	First inaccessible address, 0x00040000
x2	Store source 0x7B (123)

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

lui x1, 0x00040                # 0x00000000 | 0x000400B7
addi x2, x0, 123               # 0x00000004 | 0x07B00113
sw x2, 0(x1)                   # 0x00000008 | 0x0020A023
ebreak                         # 0x0000000C | 0x00100073

Execution

1. LUI constructs 0x00040000; ADDI sets the intended store value to 0x7B.
2. SW at 0x08 is aligned but cannot access its four-byte range, so it produces StoreAccessFault.
3. Memory is unchanged, the earlier register values remain, and PC stays at 0x08. The following EBREAK never executes; there are three attempts.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
x1	0x00040000	First inaccessible address, 0x00040000
x2	0x0000007B	Store source 0x7B (123)
PC	0x00000008	Faulting attempt address
Attempts	3	Checkpoints I0–I2
HALTED	0	No EBREAK halt
TRAPPED	1	Expected terminal exception
TRAP_CAUSE	8	StoreAccessFault, a project enum code

Start address	Bytes, in increasing address order
None	—

No data writes occur; the initial data image is unchanged. An out-of-range store is not silently discarded as a successful instruction: it terminates with a trap.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 14 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 3 instruction attempts are included, with absolute simulator time and checkpoint number. The terminal fault is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 3 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-14, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7092	LUI @ 0x00000000	raw=0x000400b7, pc_after=0x00000004, wb=x1=0x00040000, mem=None, flow=next
I1	11092	ADDI @ 0x00000004	raw=0x07b00113, pc_after=0x00000008, wb=x2=0x0000007b, mem=None, flow=next
I2	15092	SW @ 0x00000008	raw=0x0020a023, pc_after=0x00000008, wb=None, mem=Write Word @0x00040000 <- 0x0000007b fault, flow=next, trapped=true cause=StoreAccessFault

Open program 14 reference