Program 16: Instruction-fetch access fault

Program catalogue · Instruction reference · Executable reference

Purpose

Accept an aligned jump target, then trap when the following fetch cannot access instruction memory.

This is a negative test: the named trap is the expected outcome, not a failed simulation.

Setup

Property	Value
Benchmark workload ID	program-16
Headless selection	--program 16
Visualizer scenario	rv32i-program16
Registered test	RV32ISingleCycleSystemTest/program-16
Instruction image	2 words, starting at 0x00000000; last word at 0x00000004
Initial state	PC = 0x00000000; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
x1	Aligned target 0x00040000

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

lui x1, 0x00040                # 0x00000000 | 0x000400B7
jalr x0, 0(x1)                 # 0x00000004 | 0x00008067

Execution

1. LUI constructs 0x00040000, the first address beyond instruction memory.
2. JALR at 0x04 accepts this aligned target and updates PC to 0x00040000. It discards its link through rd=x0.
3. The next attempt cannot fetch four instruction bytes at that PC. It records InstructionAccessFault and keeps PC at the inaccessible target.

There are three attempts but only two loaded words: the third checkpoint is a failed fetch, not another instruction in the image. This differs from Program 15, where the jump itself is rejected and PC never reaches the target.

Expected result

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
x1	0x00040000	Aligned target 0x00040000
PC	0x00040000	Faulting attempt address
Attempts	3	Checkpoints I0–I2
HALTED	0	No EBREAK halt
TRAPPED	1	Expected terminal exception
TRAP_CAUSE	4	InstructionAccessFault, a project enum code

Start address	Bytes, in increasing address order
None	—

No data writes occur; the initial data image is unchanged. No instruction word is successfully fetched at the final PC. The faulting checkpoint must not be interpreted as a decoded instruction from memory.

Simulation and checkpoints

For a headless functional check, run build/rv32i_experiment --core single --program 16 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 3 instruction attempts are included, with absolute simulator time and checkpoint number. The terminal fault is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 3 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-16, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7092	LUI @ 0x00000000	raw=0x000400b7, pc_after=0x00000004, wb=x1=0x00040000, mem=None, flow=next
I1	11092	JALR @ 0x00000004	raw=0x00008067, pc_after=0x00040000, wb=x0=0x00000008 ignored-x0, mem=None, jump=JALR
I2	15092	INVALID @ 0x00040000	raw=0x00000000, pc_after=0x00040000, wb=None, mem=None, flow=next, trapped=true cause=InstructionAccessFault

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