Program 12: Misaligned halfword store¶

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Purpose¶

Reject an unaligned halfword store without writing either of its bytes.

This is a negative test: the named trap is the expected outcome, not a failed simulation.

Setup¶

Property	Value
Benchmark workload ID	`program-12`
Headless selection	`--program 12`
Visualizer scenario	`rv32i-program12`
Registered test	`RV32ISingleCycleSystemTest/program-12`
Instruction image	4 words, starting at `0x00000000`; last word at `0x0000000C`
Initial state	PC = `0x00000000`; all registers zero; neither halted nor trapped
Memories	Separate instruction and data memories, 256 KiB each; unlisted data bytes zero

Start address	Bytes, in increasing address order
None	—

The table lists the complete preloaded data image, not instruction bytes. No data image is required.

Register	Role established by the program
`x1`	Odd address 0x101
`x2`	Store source 0x123

The shared setup describes reset, loading, and the behavioral-core selection. These hand-written programs do not use the standard ABI stack.

Assembly¶

Every instruction word is shown, including words that a trap or branch may prevent from executing. Address and word comments identify the exact fixture image.

addi x1, x0, 0x101             # 0x00000000 | 0x10100093
addi x2, x0, 0x123             # 0x00000004 | 0x12300113
sh x2, 0(x1)                   # 0x00000008 | 0x00209023
ebreak                         # 0x0000000C | 0x00100073

Execution¶

Initialize the address to 0x101 and source value to 0x123.
SH at 0x08 requires a two-byte-aligned address. The odd address causes StoreAddressMisaligned.
Neither byte is written. Earlier register writes remain, PC stays at 0x08, and the EBREAK at 0x0C is not executed.

Three attempts occur. A rejected store must not leave a partially updated memory value.

Expected result¶

These are the fixture's explicit final-state assertions. Unlisted registers are not implicitly zero; their values follow the assembly. The store table enumerates every written byte, including zero-valued writes.

Item	Expected value	Meaning
`x1`	`0x00000101`	Odd address 0x101
`x2`	`0x00000123`	Store source 0x123
`PC`	`0x00000008`	Faulting attempt address
`Attempts`	3	Checkpoints I0–I2
`HALTED`	0	No EBREAK halt
`TRAPPED`	1	Expected terminal exception
`TRAP_CAUSE`	7	`StoreAddressMisaligned`, a project enum code

Start address	Bytes, in increasing address order
None	—

No data writes occur; the initial data image is unchanged. The store source remains 0x123, but no data bytes receive it.

Simulation and checkpoints¶

For a headless functional check, run build/rv32i_experiment --core single --program 12 --period 4000 --max-cycles 4096 --allocation-limit-mib 512. Select baseline or advanced for the same fixture on another core; add --fidelity reference for the structural-datapath reference profile. The explicit period is a scheduling choice, not a performance result. Use the campaign procedure for clock-certified measurements.

All 3 instruction attempts are included, with absolute simulator time and checkpoint number. The terminal fault is included. The table is scrollable in both directions. Observation conventions distinguish these attempts from loaded word addresses and hardware cycles.

All 3 instruction-attempt checkpoints of RV32ISingleCycleSystemTest/program-12, with a behavioral core. Times are absolute simulator units, not milliseconds or an ISA latency.

Checkpoint	Time	Instruction / address	Expected architectural effects
I0	7080	`ADDI @ 0x00000000`	`raw=0x10100093, pc_after=0x00000004, wb=x1=0x00000101, mem=None, flow=next`
I1	11080	`ADDI @ 0x00000004`	`raw=0x12300113, pc_after=0x00000008, wb=x2=0x00000123, mem=None, flow=next`
I2	15080	`SH @ 0x00000008`	`raw=0x00209023, pc_after=0x00000008, wb=None, mem=Write Halfword @0x00000101 <- 0x00000123 fault, flow=next, trapped=true cause=StoreAddressMisaligned`

Open program 12 reference