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Reinventing the Wheel
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Reinventing the Wheel
arnold518/reinventing-the-wheel
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ALU8
ALU8
2.1. Arithmetic Components
2.2. Logic Operations
2.3. Shifts and Rotations
2.4. Comparison and Selection
2.5. Flags
2.6. Complete ALU8
Memories
Memories
3.1. Memory Devices
3.1. Memory Devices
3.1.0. Helper Components
3.1.1. Flip-Flop Storage
3.1.2. SRAM
3.1.3. DRAM
3.1.4. ROM
3.1.5. NOR Flash
3.1.6. Scalable Memory Container
3.2. Memory Transactions
3.3. Memory Controllers
RV32I
RV32I
4.1. RV32I Reference
4.1. RV32I Reference
4.1.1. Machine Model
4.1.2. Formats and Decoding
4.1.3. Instruction Reference
4.1.3. Instruction Reference
Arithmetic
Logic
Shifts
Comparisons
Upper Immediates
Loads
Stores
Branches
Jumps
Ordering and System
4.1.4. Executable Reference
4.2. Benchmarking and Verification
4.2. Benchmarking and Verification
4.2.1. Architecture
4.2.2. Execution and Measurement
4.2.2. Execution and Measurement
ยง 4.2.2. Execution and Measurement
Clock Analysis
4.2.3. Fixed Programs
4.2.3. Fixed Programs
Instruction Behavior
Instruction Behavior
1. Array sum, loop, and stores
2. Arithmetic, logic, shifts, and comparisons
3. Signed and unsigned memory accesses
4. Conditional branches and fallthrough
5. Direct call, indirect jump, and return
6. Upper immediates, PC-relative values, and FENCE
7. Fibonacci sequence
8. Byte copy and checksum
Traps
Traps
9. Illegal instruction and precise stopping
10. Environment-call trap
11. Misaligned word load
12. Misaligned halfword store
13. Out-of-range word load
14. Out-of-range word store
15. Misaligned jump target
16. Instruction-fetch access fault
Workloads
Workloads
17. Independent ALU chains
18. Dependent ALU chain
19. Repeated load-use pairs
20. Branch-heavy loop
21. Sixteen-word array sum
22. Word copy and checksum
4.2.4. Generated Workloads
4.2.4. Generated Workloads
Dependent integer recurrence
Alternating branch loop
Nested counted loops
Independent ALU chains
Dependency distance
Immediate load-use pairs
Scheduled load-use pairs
Controlled branch outcomes
Predictor table aliasing
Nested direct and indirect calls
Streaming copy and checksum
Dependent pointer chasing
Unsigned insertion sort
Bitwise CRC32 kernel
Byte scan and classification
4.2.5. Compiled and External Workloads
4.2.5. Compiled and External Workloads
Self-Checking ELF Smoke
Compiled C Equivalence
Middle-Scale Compiled Equivalence
Embench Source Catalogue
Embench Source Catalogue
aha-mont64
crc32
cubic
edn
huffbench
matmult-int
minver
nbody
nettle-aes
nettle-sha256
nsichneu
picojpeg
qrduino
sglib-combined
slre
st
statemate
ud
wikisort
4.2.6. Verification
4.2.6. Verification
Infrastructure
Workload Correctness
Fidelity Equivalence
Clock and Timing
4.2.7. Campaigns and Reproducibility
4.3. RV32I Building Blocks
4.3. RV32I Building Blocks
4.3.1. Register<W>
4.3.2. Register File
4.3.3. ALU32
4.3.4. Instruction Decoder
4.3.5. Memory Access
4.3.6. Execution Control and Status
4.4. Single-Cycle Core
4.4. Single-Cycle Core
4.4.1. Fetch
4.4.2. Decode and Register Read
4.4.3. Execute
4.4.4. Memory Access
4.4.5. Writeback
4.4.6. Next PC
4.4.7. Complete Core
4.5. Baseline Pipeline
4.5. Baseline Pipeline
4.5.1. Pipeline Registers
4.5.2. Fetch
4.5.3. Decode and Register Read
4.5.4. Execute
4.5.5. Memory Access
4.5.6. Writeback and Retirement
4.5.7. Dependencies and Control
4.5.8. Complete Core
4.6. Advanced Pipeline
4.6. Advanced Pipeline
4.6.1. Operand Forwarding
4.6.2. Load-Use Hazards
4.6.3. Branch Prediction
4.6.4. Prediction Recovery
4.6.5. Memory Wait Handling
4.6.6. Complete Advanced Core
4.7. Experiment Results
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