§ 4.4.5. Writeback

RV32ISingleCycleWritebackStage selects a destination-register value. In the core it is named WRITEBACK. It contains no register file or clock: the physical write port belongs to Decode.

Component	Description	Structural	Behavioral
RV32ISingleCycleWritebackStage	Select zero, ALU result, load data, or link value	Yes	Yes

4.4.5.1. RV32ISingleCycleWritebackStage

IO pins

Pin	Direction	Width	Description
ALU_RESULT	Input	32	Arithmetic/logic/address result from Execute
READ_DATA	Input	32	Formatted load value from Memory
PC_PLUS_4	Input	32	Link value computed by Fetch
WRITEBACK_SEL	Input	2	Source selector
WB_VALUE	Output	32	Selected register write value

Behavior

WRITEBACK_SEL	WB_VALUE	Typical use
0	Zero	Instructions without register writeback
1	ALU_RESULT	Arithmetic, logic, shifts, comparisons, LUI, AUIPC
2	READ_DATA	Loads
3	PC_PLUS_4	JAL/JALR return address

Every two-bit selector is defined. Selection does not authorize a write. WB_VALUE may change while the combinational path settles; only the final value is captured at the edge when execution status permits REGISTER_WRITE. A no-write instruction can have any WB_VALUE without changing a register. There is no saturation, sign conversion, additional arithmetic, or pending-memory state here.

C++ example

#include <cstdint>
namespace single_cycle_example {
struct WritebackInputs {
    uint32_t ALU_RESULT, READ_DATA, PC_PLUS_4;
    unsigned WRITEBACK_SEL;
};
struct WritebackOutputs { uint32_t WB_VALUE; };
WritebackOutputs writeback(const WritebackInputs& i) {
    const uint32_t sources[]{0,i.ALU_RESULT,i.READ_DATA,i.PC_PLUS_4};
    return {sources[i.WRITEBACK_SEL]}; // Selector must fit its two-bit pin.
}
}

Unknown inputs and timing

For a known selector, the behavioral model copies the selected bit vector (or emits zero for selector 0), preserving selected X/Z bits. An unknown selector makes its output X. Structural mux logic can resolve or transform X/Z differently; the registered equivalence scope is settled binary values. Neither implementation stores a result. A catalog-selected behavioral output uses the mux tree’s characterized delay, shortened to its actual settling time when a delay twin can answer. Structural fidelity exposes each mux transition.

Implementation

Structural implementation

RESULT_SELECT is Mux4to1_32bit. ZERO32 drives its input 0; the three result pins drive inputs 1–3. The selector is the decoder's two-bit writeback control.

Behavioral implementation

BehavioralStage's Writeback branch selects the same input vector directly. The family is rv32i.single-cycle.writeback.

Examples

The four selections use distinct ALU/load/link patterns so a swapped source cannot pass by coincidence. The initial setup row is also included.

All 5 recorded rows of RV32ISingleCycleWritebackStageTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (b2ac673687c3ee66). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	ALU_RESULTInput · 32 bit	PC_PLUS_4Input · 32 bit	READ_DATAInput · 32 bit	WRITEBACK_SELInput · 2 bit	WB_VALUEExpected output · 32 bit
#0inputs	5	0xDEADBEEF	0x00000104	0x80000000	0x0	not checked
#1select-0	6	0xDEADBEEF	0x00000104	0x80000000	0x0	0x00000000
#2select-1	12	0xDEADBEEF	0x00000104	0x80000000	0x1	0xDEADBEEF
#3select-2	19	0xDEADBEEF	0x00000104	0x80000000	0x2	0x80000000
#4select-3	26	0xDEADBEEF	0x00000104	0x80000000	0x3	0x00000104

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open Writeback stage

Tests

RV32ISingleCycleWritebackStageTest covers every selector in both implementations. The integration test checks load, ALU, and JALR link writes without updating registers early. RV32ISingleCycleDocumentationTest.py compiles/replays this example. Source: RV32ISingleCycleStages.cpp and RV32ISingleCycleStagesBehavioral.cpp; scenarios: src/tests/RV32ISingleCycleStageTests.cpp.