§ 4.3.4. Instruction Decoder

These components translate a 32-bit instruction into datapath controls. 4.1 defines instruction semantics; this page specifies the actual circuit outputs, recognition rules, and implementation boundaries. Decoding does not read registers, access memory, or execute the instruction.

The single-cycle Decode stage places RV32IDecodeControlUnit at CORE.DECODE.CONTROL next to the register file. The stage adds operand values and the writeback port while forwarding all decoder outputs unchanged. REG_WRITE remains intent, distinct from the stage's qualified REGISTER_WRITE input.

Component	Description	Structural	Behavioral
RV32IBitPatternMatcher	Parameterized masked instruction recognition	Yes	No
RV32IDecodeControlUnit	Register fields, immediate, legality, and execution controls	Yes	Yes

Columns describe registered implementations. C++ examples describe settled binary values, omitting gate delays and X/Z.

4.3.4.1. RV32IBitPatternMatcher

IO pins

Pin	Direction	Width	Description
INPUT	Input	32	Word to inspect
MATCH	Output	1	All selected bits equal the configured value

mask and value are construction parameters, not pins. A one in mask selects a bit to compare. value is masked at construction; bits outside the mask are irrelevant. A zero mask is rejected.

Behavior

The predicate is (INPUT & mask) == (value & mask). For example, mask 0x0000707f and value 0x00002003 recognize the opcode/funct3 of LW, regardless of its register and immediate fields.

C++ example

#include <cstdint>
#include <stdexcept>
namespace decode_example {
bool match(uint32_t input, uint32_t mask, uint32_t value) {
    if (!mask) throw std::invalid_argument("mask must select a bit");
    return (input & mask) == (value & mask);
}
}

Unknown inputs and timing

Unmasked bits cannot affect MATCH. A known mismatch can mask an unknown selected bit. Selected zero-valued pattern bits use NOT gates; their X/Z inputs become X. With exactly one selected bit whose expected value is one, the output is a direct wire and can retain Z. Multi-term matches pass through AND gates. Timing depends on the number of selected terms.

Implementation

Structural implementation

INPUT_SPLIT exposes the bits, NOT gates invert selected zero-pattern terms, and an AND chain combines them. There is no registered behavioral implementation.

Examples

All 8 recorded rows of RV32IBitPatternMatcherTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (a820042d14b9ff55). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	INPUTInput · 32 bit	MATCHExpected output · 1 bit
#0row-0	6	0x00002003	1
#1row-1	8	0xFFF32283	1
#2row-2	15	0x00001003	0
#3row-3	20	0x00002023	0
#4row-4	27	0bX0000000000000000010000000000011	1
#5row-5	29	0bZ0000000000000000010000000000011	1
#6row-6	36	0b0000000000000000001X000000000011	X
#7row-7	41	0b0000000000000000011X000000000011	0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open pattern matcher

Tests

RV32IBitPatternMatcherTest covers several mask/value configurations, ignored bits, selected X/Z, mismatch masking, and rejection of a zero mask. The table/embedded run show the selected scenario; the registered native test runs every parameterized scenario.

4.3.4.2. RV32IDecodeControlUnit

IO pins

Pin	Direction	Width	Description
INSTRUCTION	Input	32	Complete instruction word
RS1_ADDR, RS2_ADDR, RD_ADDR	Output	5 each	Raw bits 19:15, 24:20, 11:7
IMM	Output	32	Constructed immediate; zero if unused or illegal
ALU_OP	Output	5	ALU32 operation
ALU_A_SEL	Output	2	0: RS1; 1: PC; 2: zero
ALU_B_SEL	Output	2	0: RS2; 1: immediate; 2: zero
LEGAL	Output	1	Recognized supported instruction
REG_WRITE	Output	1	Register write intent, not final commit enable
MEM_READ, MEM_WRITE	Output	1 each	Load/store intent
WRITEBACK_SEL	Output	2	0: none; 1: ALU; 2: memory; 3: PC+4
MEM_SIZE	Output	2	0: byte; 1: halfword; 2: word/default
LOAD_SIGN_EXTEND	Output	1	Signed byte/halfword load
USES_RS1, USES_RS2	Output	1 each	Whether raw source fields are actual dependencies
BRANCH_TYPE	Output	3	0: none; 1: BEQ; 2: BNE; 3: BLT; 4: BGE; 5: BLTU; 6: BGEU
JUMP_TYPE	Output	2	0: none; 1: JAL; 2: JALR
HALT_REQUEST	Output	1	Project EBREAK convention
TRAP_REQUEST	Output	1	Illegal instruction or ECALL
DECODE_TRAP_CAUSE	Output	4	0: none; 1: illegal instruction; 2: environment call

Behavior

Register fields are always raw slices, even when unused or illegal. For example, RS2_ADDR in an immediate instruction contains immediate bits; USES_RS2=0 says not to read it as a dependency. REG_WRITE remains high for instructions targeting x0: the register file suppresses that write.

Recognition and control groups

Numbers in the opcode/funct columns below are hexadecimal. All listed restrictions must match. Register and immediate fields are otherwise unrestricted.

Group	Opcode / funct restriction	Recognized instructions	Main controls
Register ALU	33; funct7=00, funct3=0,1,2,3,4,5,6,7; additionally funct7=20, funct3=0,5	ADD, SLL, SLT, SLTU, XOR, SRL, OR, AND; SUB, SRA	RS1/RS2 → ALU; register write, ALU writeback
Immediate ALU	13; funct3=0,2,3,4,6,7	ADDI, SLTI, SLTIU, XORI, ORI, ANDI	RS1/I-immediate → ALU; register write, ALU writeback
Immediate shifts	13; funct3=1, funct7=00; or funct3=5, funct7=00,20	SLLI, SRLI, SRAI	Same as immediate ALU; ALU uses low five immediate bits
Loads	03; funct3=0,1,2,4,5	LB, LH, LW, LBU, LHU	RS1 + I-immediate; memory read and memory writeback
Stores	23; funct3=0,1,2	SB, SH, SW	RS1 + S-immediate; memory write; RS2 is store data
Branches	63; funct3=0,1,4,5,6,7	BEQ, BNE, BLT, BGE, BLTU, BGEU	RS1 − RS2; B-immediate and branch selector; no register write
PC-relative jump	6f	JAL	PC + J-immediate; jump=1; PC+4 writeback
Register-relative jump	67; funct3=0	JALR	RS1 + I-immediate; jump=2; PC+4 writeback
Upper immediate	37 / 17	LUI / AUIPC	Zero + PASS_B / PC + ADD; U-immediate; ALU writeback
Fence	0f; funct3=0	FENCE	Legal no-op in this simulator; I-immediate still exposed
Exact system word	00000073 / 00100073	ECALL / EBREAK	Trap cause 2 / halt request; I-immediate 0 / 1

These rules recognize 40 instruction forms. FENCE accepts all other fields under its opcode/funct3 mask; it does not implement ordering in a cache hierarchy. FENCE.I, CSR instructions, M-extension instructions, and other unmatched encodings are illegal here. EBREAK halts the simulator; this is not a privileged breakpoint exception implementation.

For an illegal word: LEGAL=0, TRAP_REQUEST=1, cause=1, ALU_OP=12, both ALU sources=2, MEM_SIZE=2; immediate and all other control outputs are zero. Raw register fields remain exposed. Control encodings not listed above are never emitted for binary instructions.

C++ example

The following reference includes every recognized group, immediate construction, and illegal fallback. Immediate values are 32-bit two's-complement bit patterns. SRAI exposes the complete I-immediate (including its function bits); only the low five bits reach the shift distance.

#include <array>
namespace decode_example {
struct Decoded {
    uint32_t RS1_ADDR=0, RS2_ADDR=0, RD_ADDR=0, IMM=0;
    unsigned ALU_OP=12, ALU_A_SEL=2, ALU_B_SEL=2, WRITEBACK_SEL=0, MEM_SIZE=2;
    unsigned BRANCH_TYPE=0, JUMP_TYPE=0, DECODE_TRAP_CAUSE=1;
    bool LEGAL=false, REG_WRITE=false, MEM_READ=false, MEM_WRITE=false;
    bool LOAD_SIGN_EXTEND=false, USES_RS1=false, USES_RS2=false;
    bool HALT_REQUEST=false, TRAP_REQUEST=true;
};
uint32_t sext(uint32_t x, unsigned width) {
    const uint32_t sign = uint32_t{1} << (width-1);
    return (x ^ sign) - sign; // x has already been masked to width bits.
}
Decoded decode(uint32_t w) {
    Decoded d;
    d.RS1_ADDR=(w>>15)&31; d.RS2_ADDR=(w>>20)&31; d.RD_ADDR=(w>>7)&31;
    const auto invalid=d;
    const unsigned op=w&127, f3=(w>>12)&7, f7=w>>25;
    const uint32_t i=sext(w>>20,12);
    const uint32_t s=sext(((w>>25)<<5)|((w>>7)&31),12);
    const uint32_t b=sext(((w>>31)<<12)|(((w>>7)&1)<<11)|(((w>>25)&63)<<5)|(((w>>8)&15)<<1),13);
    const uint32_t u=w&0xfffff000U;
    const uint32_t j=sext(((w>>31)<<20)|(((w>>12)&255)<<12)|(((w>>20)&1)<<11)|(((w>>21)&1023)<<1),21);
    d.LEGAL=true; d.TRAP_REQUEST=false; d.DECODE_TRAP_CAUSE=0;
    const auto reg = [&](unsigned alu, unsigned a, unsigned src_b, uint32_t imm) {
        d.ALU_OP=alu; d.ALU_A_SEL=a; d.ALU_B_SEL=src_b; d.IMM=imm;
        d.REG_WRITE=true; d.WRITEBACK_SEL=1;
        d.USES_RS1=a==0; d.USES_RS2=src_b==0;
    };
    const std::array<unsigned,8> alu{0,5,8,9,4,6,3,2};
    if (op==0x33) {
        if (f7!=0 && !(f7==0x20 && (f3==0 || f3==5))) return invalid;
        reg(f7 ? (f3==0 ? 1 : 7) : alu[f3],0,0,0);
    } else if (op==0x13) {
        if (f3==1 && f7!=0) return invalid;
        if (f3==5 && f7!=0 && f7!=0x20) return invalid;
        reg(f3==5 && f7==0x20 ? 7 : alu[f3],0,1,i);
    } else if (op==0x03) {
        if (!(f3==0 || f3==1 || f3==2 || f3==4 || f3==5)) return invalid;
        reg(0,0,1,i); d.MEM_READ=true; d.WRITEBACK_SEL=2;
        d.MEM_SIZE=f3&3; d.LOAD_SIGN_EXTEND=f3<2;
    } else if (op==0x23) {
        if (f3>2) return invalid;
        d.ALU_OP=0; d.ALU_A_SEL=0; d.ALU_B_SEL=1; d.IMM=s;
        d.MEM_WRITE=true; d.MEM_SIZE=f3; d.USES_RS1=d.USES_RS2=true;
    } else if (op==0x63) {
        const std::array<unsigned,8> branch{1,2,0,0,3,4,5,6};
        if (!branch[f3]) return invalid;
        d.ALU_OP=1; d.ALU_A_SEL=d.ALU_B_SEL=0; d.IMM=b;
        d.BRANCH_TYPE=branch[f3]; d.USES_RS1=d.USES_RS2=true;
    } else if (op==0x6f) {
        reg(0,1,1,j); d.JUMP_TYPE=1; d.WRITEBACK_SEL=3;
    } else if (op==0x67 && f3==0) {
        reg(0,0,1,i); d.JUMP_TYPE=2; d.WRITEBACK_SEL=3;
    } else if (op==0x37) reg(11,2,1,u);
    else if (op==0x17) reg(0,1,1,u);
    else if (op==0x0f && f3==0) d.IMM=i;
    else if (w==0x00000073) { d.TRAP_REQUEST=true; d.DECODE_TRAP_CAUSE=2; }
    else if (w==0x00100073) { d.HALT_REQUEST=true; d.IMM=1; }
    else return invalid;
    return d;
}
}

Unknown inputs and timing

The structural decoder handles each predicate and rewired field separately: unknown unused bits need not destroy recognition, and known register bits can remain visible. RV32IDecodeControlBehavioral is deliberately conservative: any nonbinary instruction bit makes all outputs X. Its registered equivalence scope is binary, settled output values. No instruction is latched here; downstream state must wait for decoding to settle.

Implementation

Structural implementation

The top level has five children, arranged by connectivity:

Child	Responsibility
FIELDS_AND_IMMEDIATES	Rewire the register addresses and I/S/B/U/J immediate forms
RECOGNITION	Shared opcode/funct3/funct7 predicates and instruction AND terms; exact ECALL/EBREAK matches
CONTROL_SIGNALS	Eighteen named control-output fields, each containing its own bit equations
IMMEDIATE_MUX	Select the immediate format specified by IMMEDIATE_SELECT
CONST_ZERO32	Zero for unused immediate selections

Rewire is a fixed bit-to-bit wiring map, configured when the component is constructed. Each mapped output bit copies one specified input bit. It can extract fields, rearrange bits, join or split buses, and fan one input bit out to several destinations (including sign extension). Unmapped output bits use the configured 0, 1, or X default; this instance uses 0. It has no stored state, runtime selection input, arithmetic, or added simulation delay. Mapped X and Z values are copied unchanged. A destination bit cannot have two mapping sources.

Here FIELDS_AND_IMMEDIATES constructs every immediate form in parallel; IMMEDIATE_MUX, not Rewire, selects the form needed by the decoded instruction. The visualization shows one INSTRUCTION[32] spine with separate field taps. Tap expressions list output bits from most significant to least significant: [h:l] selects input bits, braces concatenate fields, and n× repeats a bit.

Output	Example tap expression	Meaning
RS1[5]	[19:15]	Extract the source-register field
RD[5]	[11:7]	Extract the destination-register field
IMM_I[32]	{20×[31], [31:20]}	Copy the 12-bit immediate and repeat its sign bit
IMM_U[32]	{[31:12], 12×0}	Copy the upper 20 bits and fill the low 12 bits with zero

RV32IInstructionRecognition has an INSTRUCTION[32] input and forty one-hot match lines, bundled as MATCH_LO[32] and MATCH_HI[8] in the source pattern-table order. These are instruction indicators, not an encoded instruction number. RV32IDecodeControlSignals consumes those bundles and produces the public controls plus the internal IMMEDIATE_SELECT[3]. Its RV32IDecodeControlField<name> children each expose the same match inputs and an OUT bus of the corresponding control width.

These helpers are fixed structural implementations, not additional behavioral variants. Expanding them reveals shared pattern matchers, recognition AND gates, and balanced OR/NOT control equations. Repeated output terms are shared; each OR reduction keeps the same settled logic and safe illegal default without a long serial chain. Field layouts keep each bit equation together in numeric order; no logic is replaced by a lookup-table black box.

Behavioral implementation

RV32IDecodeControlBehavioral uses RV32IDecoder::decode and RV32IControl::fromDecoded, converts their enums to the public pin encodings, and publishes outputs using gate-derived, output-specific delays when selected through the catalog. It is registered under rv32i.decode-control alongside the structural implementation.

Examples

All 116 recorded rows of RV32IDecodeControlUnitTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (1132228895dfd733). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	INSTRUCTIONInput · 32 bit	ALU_A_SELExpected output · 2 bit	ALU_B_SELExpected output · 2 bit	ALU_OPExpected output · 5 bit	BRANCH_TYPEExpected output · 3 bit	DECODE_TRAP_CAUSEExpected output · 4 bit	HALT_REQUESTExpected output · 1 bit	IMMExpected output · 32 bit	JUMP_TYPEExpected output · 2 bit	LEGALExpected output · 1 bit	LOAD_SIGN_EXTENDExpected output · 1 bit	MEM_READExpected output · 1 bit	MEM_SIZEExpected output · 2 bit	MEM_WRITEExpected output · 1 bit	RD_ADDRExpected output · 5 bit	REG_WRITEExpected output · 1 bit	RS1_ADDRExpected output · 5 bit	RS2_ADDRExpected output · 5 bit	TRAP_REQUESTExpected output · 1 bit	USES_RS1Expected output · 1 bit	USES_RS2Expected output · 1 bit	WRITEBACK_SELExpected output · 2 bit
#0add	18	0x00C58533	0x0	0x0	0x00	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#1subtract	28	0x40C58533	0x0	0x0	0x01	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#2shift-left-logical	42	0x00C59533	0x0	0x0	0x05	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#3set-less-than	56	0x00C5A533	0x0	0x0	0x08	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#4set-less-than-unsigned	66	0x00C5B533	0x0	0x0	0x09	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#5exclusive-or	80	0x00C5C533	0x0	0x0	0x04	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#6shift-right-logical	90	0x00C5D533	0x0	0x0	0x06	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#7shift-right-arithmetic	100	0x40C5D533	0x0	0x0	0x07	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#8or	114	0x00C5E533	0x0	0x0	0x03	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#9and	125	0x00C5F533	0x0	0x0	0x02	0x0	0x0	0	0x00000000	0x0	1	0	0	0x2	0	0x0A	1	0x0B	0x0C	0	1	1	0x1
#10add-immediate	144	0xFFF28313	0x0	0x1	0x00	0x0	0x0	0	0xFFFFFFFF	0x0	1	0	0	0x2	0	0x06	1	0x05	0x1F	0	1	0	0x1
#11set-less-than-immediate	156	0x8002A313	0x0	0x1	0x08	0x0	0x0	0	0xFFFFF800	0x0	1	0	0	0x2	0	0x06	1	0x05	0x00	0	1	0	0x1
#12set-less-than-immediate-unsigned	166	0x7FF2B313	0x0	0x1	0x09	0x0	0x0	0	0x000007FF	0x0	1	0	0	0x2	0	0x06	1	0x05	0x1F	0	1	0	0x1
#13exclusive-or-immediate	184	0x0552C313	0x0	0x1	0x04	0x0	0x0	0	0x00000055	0x0	1	0	0	0x2	0	0x06	1	0x05	0x15	0	1	0	0x1
#14or-immediate	195	0x1232E313	0x0	0x1	0x03	0x0	0x0	0	0x00000123	0x0	1	0	0	0x2	0	0x06	1	0x05	0x03	0	1	0	0x1
#15and-immediate	205	0x3212F313	0x0	0x1	0x02	0x0	0x0	0	0x00000321	0x0	1	0	0	0x2	0	0x06	1	0x05	0x01	0	1	0	0x1
#16shift-left-logical-immediate	224	0x00529313	0x0	0x1	0x05	0x0	0x0	0	0x00000005	0x0	1	0	0	0x2	0	0x06	1	0x05	0x05	0	1	0	0x1
#17shift-right-logical-immediate	234	0x0062D313	0x0	0x1	0x06	0x0	0x0	0	0x00000006	0x0	1	0	0	0x2	0	0x06	1	0x05	0x06	0	1	0	0x1
#18shift-right-arithmetic-immediate	245	0x41F2D313	0x0	0x1	0x07	0x0	0x0	0	0x0000041F	0x0	1	0	0	0x2	0	0x06	1	0x05	0x1F	0	1	0	0x1
#19load-byte	264	0xFF018203	0x0	0x1	0x00	0x0	0x0	0	0xFFFFFFF0	0x0	1	1	1	0x0	0	0x04	1	0x03	0x10	0	1	0	0x2
#20load-halfword	275	0x01219203	0x0	0x1	0x00	0x0	0x0	0	0x00000012	0x0	1	1	1	0x1	0	0x04	1	0x03	0x12	0	1	0	0x2
#21load-word	293	0x0141A203	0x0	0x1	0x00	0x0	0x0	0	0x00000014	0x0	1	0	1	0x2	0	0x04	1	0x03	0x14	0	1	0	0x2
#22load-byte-unsigned	311	0x0151C203	0x0	0x1	0x00	0x0	0x0	0	0x00000015	0x0	1	0	1	0x0	0	0x04	1	0x03	0x15	0	1	0	0x2
#23load-halfword-unsigned	320	0x0161D203	0x0	0x1	0x00	0x0	0x0	0	0x00000016	0x0	1	0	1	0x1	0	0x04	1	0x03	0x16	0	1	0	0x2
#24store-byte	340	0xFE838623	0x0	0x1	0x00	0x0	0x0	0	0xFFFFFFEC	0x0	1	0	0	0x0	1	0x0C	0	0x07	0x08	0	1	1	0x0
#25store-halfword	348	0x00839C23	0x0	0x1	0x00	0x0	0x0	0	0x00000018	0x0	1	0	0	0x1	1	0x18	0	0x07	0x08	0	1	1	0x0
#26store-word	363	0x0083AE23	0x0	0x1	0x00	0x0	0x0	0	0x0000001C	0x0	1	0	0	0x2	1	0x1C	0	0x07	0x08	0	1	1	0x0
#27branch-equal	379	0x00208863	0x0	0x0	0x01	0x1	0x0	0	0x00000010	0x0	1	0	0	0x2	0	0x10	0	0x01	0x02	0	1	1	0x0
#28branch-not-equal	389	0xFE209EE3	0x0	0x0	0x01	0x2	0x0	0	0xFFFFFFFC	0x0	1	0	0	0x2	0	0x1D	0	0x01	0x02	0	1	1	0x0
#29branch-less-than	407	0x0220C063	0x0	0x0	0x01	0x3	0x0	0	0x00000020	0x0	1	0	0	0x2	0	0x00	0	0x01	0x02	0	1	1	0x0
#30branch-greater-or-equal	418	0xFE20D0E3	0x0	0x0	0x01	0x4	0x0	0	0xFFFFFFE0	0x0	1	0	0	0x2	0	0x01	0	0x01	0x02	0	1	1	0x0
#31branch-less-than-unsigned	436	0x0420E063	0x0	0x0	0x01	0x5	0x0	0	0x00000040	0x0	1	0	0	0x2	0	0x00	0	0x01	0x02	0	1	1	0x0
#32branch-greater-or-equal-unsigned	448	0xFC20F0E3	0x0	0x0	0x01	0x6	0x0	0	0xFFFFFFC0	0x0	1	0	0	0x2	0	0x01	0	0x01	0x02	0	1	1	0x0
#33jump-and-link	465	0x800002EF	0x1	0x1	0x00	0x0	0x0	0	0xFFF00000	0x1	1	0	0	0x2	0	0x05	1	0x00	0x00	0	0	0	0x3
#34jump-and-link-register	484	0xFF4280E7	0x0	0x1	0x00	0x0	0x0	0	0xFFFFFFF4	0x2	1	0	0	0x2	0	0x01	1	0x05	0x14	0	1	0	0x3
#35load-upper-immediate	502	0x123454B7	0x2	0x1	0x0B	0x0	0x0	0	0x12345000	0x0	1	0	0	0x2	0	0x09	1	0x08	0x03	0	0	0	0x1
#36add-upper-immediate-to-pc	514	0xFFFFF497	0x1	0x1	0x00	0x0	0x0	0	0xFFFFF000	0x0	1	0	0	0x2	0	0x09	1	0x1F	0x1F	0	0	0	0x1
#37fence	533	0x0FF0000F	0x2	0x2	0x0C	0x0	0x0	0	0x000000FF	0x0	1	0	0	0x2	0	0x00	0	0x00	0x1F	0	0	0	0x0
#38environment-call	549	0x00000073	0x2	0x2	0x0C	0x0	0x2	0	0x00000000	0x0	1	0	0	0x2	0	0x00	0	0x00	0x00	1	0	0	0x0
#39breakpoint	561	0x00100073	0x2	0x2	0x0C	0x0	0x0	1	0x00000001	0x0	1	0	0	0x2	0	0x00	0	0x00	0x01	0	0	0	0x0
#40illegal-instruction-length	573	0x00000000	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x00	0x00	1	0	0	0x0
#41illegal-unknown-opcode	589	0x0000007B	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x00	0x00	1	0	0	0x0
#42illegal-rv64-op-immediate	596	0x0000811B	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x02	0	0x01	0x00	1	0	0	0x0
#43illegal-register-funct7	604	0x022081B3	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x03	0	0x01	0x02	1	0	0	0x0
#44illegal-shift-funct7	612	0x0250D113	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x02	0	0x01	0x05	1	0	0	0x0
#45illegal-branch-funct3	619	0x0020A263	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x04	0	0x01	0x02	1	0	0	0x0
#46illegal-load-funct3	627	0x0000B103	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x02	0	0x01	0x00	1	0	0	0x0
#47illegal-store-funct3	635	0x0020B023	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x01	0x02	1	0	0	0x0
#48illegal-jalr-funct3	654	0x00009167	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x02	0	0x01	0x00	1	0	0	0x0
#49illegal-fence-i	661	0x0000100F	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x00	0x00	1	0	0	0x0
#50illegal-csr	669	0x00101073	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x00	0x01	1	0	0	0x0
#51illegal-system-operation	677	0x00200073	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x00	0x02	1	0	0	0x0
#52deterministic-raw-0	684	0x06B0B208	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x04	0	0x01	0x0B	1	0	0	0x0
#53deterministic-raw-1	691	0x5D1F2DC7	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1B	0	0x1E	0x11	1	0	0	0x0
#54deterministic-raw-2	698	0xDBB0907A	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x01	0x1B	1	0	0	0x0
#55deterministic-raw-3	705	0xD9E0E591	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0B	0	0x01	0x1E	1	0	0	0x0
#56deterministic-raw-4	712	0x537B61BC	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x03	0	0x16	0x17	1	0	0	0x0
#57deterministic-raw-5	719	0x2DFFD1EB	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x03	0	0x1F	0x1F	1	0	0	0x0
#58deterministic-raw-6	726	0x00033E4E	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1C	0	0x06	0x00	1	0	0	0x0
#59deterministic-raw-7	733	0x9D0A3155	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x02	0	0x14	0x10	1	0	0	0x0
#60deterministic-raw-8	740	0x16E852B0	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x05	0	0x10	0x0E	1	0	0	0x0
#61deterministic-raw-9	747	0x0A5D464F	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0C	0	0x1A	0x05	1	0	0	0x0
#62deterministic-raw-10	754	0xCAE5FF62	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1E	0	0x0B	0x0E	1	0	0	0x0
#63deterministic-raw-11	761	0x1E6FF759	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0E	0	0x1F	0x06	1	0	0	0x0
#64deterministic-raw-12	768	0x8C5CF8E4	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x11	0	0x19	0x05	1	0	0	0x0
#65deterministic-raw-13	775	0xB6966EF3	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1D	0	0x0C	0x09	1	0	0	0x0
#66deterministic-raw-14	782	0x480267B6	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0F	0	0x04	0x00	1	0	0	0x0
#67deterministic-raw-15	789	0xFAA6BB9D	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x17	0	0x0D	0x0A	1	0	0	0x0
#68deterministic-raw-16	796	0xB7FC0858	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x10	0	0x18	0x1F	1	0	0	0x0
#69deterministic-raw-17	803	0xD0266FD7	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1F	0	0x0C	0x02	1	0	0	0x0
#70deterministic-raw-18	810	0x0AF14B4A	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x16	0	0x02	0x0F	1	0	0	0x0
#71deterministic-raw-19	817	0x48E94221	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x04	0	0x12	0x0E	1	0	0	0x0
#72deterministic-raw-20	824	0x55D9750C	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0A	0	0x12	0x1D	1	0	0	0x0
#73deterministic-raw-21	831	0xAB48ACFB	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x19	0	0x11	0x14	1	0	0	0x0
#74deterministic-raw-22	838	0xC88EBE1E	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1C	0	0x1D	0x08	1	0	0	0x0
#75deterministic-raw-23	845	0xDC5C8EE5	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1D	0	0x19	0x05	1	0	0	0x0
#76deterministic-raw-24	852	0x426E7300	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x06	0	0x1C	0x06	1	0	0	0x0
#77deterministic-raw-25	859	0xD8DCCA5F	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x14	0	0x19	0x0D	1	0	0	0x0
#78deterministic-raw-26	866	0xFB8E1432	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x08	0	0x1C	0x18	1	0	0	0x0
#79deterministic-raw-27	873	0x9793E5E9	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0B	0	0x07	0x19	1	0	0	0x0
#80deterministic-raw-28	880	0x504D7634	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0C	0	0x1A	0x04	1	0	0	0x0
#81deterministic-raw-29	899	0xB88AAC03	0x0	0x1	0x00	0x0	0x0	0	0xFFFFFB88	0x0	1	0	1	0x2	0	0x18	1	0x15	0x08	0	1	0	0x2
#82deterministic-raw-30	916	0xA84DE186	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x03	0	0x1B	0x04	1	0	0	0x0
#83deterministic-raw-31	923	0xD654CB2D	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x16	0	0x09	0x05	1	0	0	0x0
#84deterministic-raw-32	930	0xBF1632A8	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x05	0	0x0C	0x11	1	0	0	0x0
#85deterministic-raw-33	937	0xBB2675E7	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0B	0	0x0C	0x12	1	0	0	0x0
#86deterministic-raw-34	944	0x93EBFA1A	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x14	0	0x17	0x1E	1	0	0	0x0
#87deterministic-raw-35	951	0x319B02B1	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x05	0	0x16	0x19	1	0	0	0x0
#88deterministic-raw-36	958	0xC7A99C5C	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x18	0	0x13	0x1A	1	0	0	0x0
#89deterministic-raw-37	965	0x39548C0B	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x18	0	0x09	0x15	1	0	0	0x0
#90deterministic-raw-38	972	0x829971EE	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x03	0	0x12	0x09	1	0	0	0x0
#91deterministic-raw-39	979	0x21DC9075	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x00	0	0x19	0x1D	1	0	0	0x0
#92deterministic-raw-40	986	0xF19DE750	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0E	0	0x1B	0x19	1	0	0	0x0
#93deterministic-raw-41	1005	0x026D926F	0x1	0x1	0x00	0x0	0x0	0	0x000D9026	0x1	1	0	0	0x2	0	0x04	1	0x1B	0x06	0	0	0	0x3
#94deterministic-raw-42	1021	0x512E9D02	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1A	0	0x1D	0x12	1	0	0	0x0
#95deterministic-raw-43	1028	0x438DB879	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x10	0	0x1B	0x18	1	0	0	0x0
#96deterministic-raw-44	1035	0x25F28784	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0F	0	0x05	0x1F	1	0	0	0x0
#97deterministic-raw-45	1054	0x07A26D13	0x0	0x1	0x03	0x0	0x0	0	0x0000007A	0x0	1	0	0	0x2	0	0x1A	1	0x04	0x1A	0	1	0	0x1
#98deterministic-raw-46	1070	0xFDFF0F56	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1E	0	0x1E	0x1F	1	0	0	0x0
#99deterministic-raw-47	1077	0x41E4FEBD	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1D	0	0x09	0x1E	1	0	0	0x0
#100deterministic-raw-48	1084	0xB30430F8	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x01	0	0x08	0x10	1	0	0	0x0
#101deterministic-raw-49	1091	0xC7603FF7	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1F	0	0x00	0x16	1	0	0	0x0
#102deterministic-raw-50	1098	0xF4ED9CEA	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x19	0	0x1B	0x0E	1	0	0	0x0
#103deterministic-raw-51	1105	0xABDF2741	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0E	0	0x1E	0x1D	1	0	0	0x0
#104deterministic-raw-52	1112	0xB5C0D7AC	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0F	0	0x01	0x1C	1	0	0	0x0
#105deterministic-raw-53	1119	0x5CF46F1B	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1E	0	0x08	0x0F	1	0	0	0x0
#106deterministic-raw-54	1126	0x32C059BE	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x13	0	0x00	0x0C	1	0	0	0x0
#107deterministic-raw-55	1133	0x37833605	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0C	0	0x06	0x18	1	0	0	0x0
#108deterministic-raw-56	1140	0x9C1BAFA0	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1F	0	0x17	0x01	1	0	0	0x0
#109deterministic-raw-57	1159	0x58709E7F	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1C	0	0x01	0x07	1	0	0	0x0
#110deterministic-raw-58	1166	0x13B499D2	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x13	0	0x09	0x1B	1	0	0	0x0
#111deterministic-raw-59	1173	0x37666F09	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x1E	0	0x0C	0x16	1	0	0	0x0
#112deterministic-raw-60	1180	0xB4C12CD4	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x19	0	0x02	0x0C	1	0	0	0x0
#113deterministic-raw-61	1187	0xC2CEB223	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x04	0	0x1D	0x0C	1	0	0	0x0
#114deterministic-raw-62	1194	0xE152F126	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x02	0	0x05	0x15	1	0	0	0x0
#115deterministic-raw-63	1201	0x4670564D	0x2	0x2	0x0C	0x0	0x1	0	0x00000000	0x0	0	0	0	0x2	0	0x0C	0	0x00	0x07	1	0	0	0x0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open instruction decoder

Tests

RV32IDecodeControlUnitTest checks circuit outputs in both fidelities; RV32IDecoderTest and RV32IControlTest exercise the semantic helpers. RV32IBuildingBlocksDocumentationTest compiles the reference above and compares its complete output set with the declared binary circuit rows and an additional encoding sweep. The structural source is src/modules/rv32i/RV32IDecodeControlUnit.cpp; recognition tests are in src/tests/RV32IDecoderTests.cpp.