§ 3.1.0. Helper Components

Reusable addressing, selection, and output circuitry for the memory-device architecture. These components do not store memory words, buffer transactions, or define a common storage-cell interface.

Component	Description	Structural	Behavioral
MatrixRowDecoder<R>	Select one row from a full 32-bit row address	Yes	No
MatrixColumnMux<W,K>	Select one W-bit word from K words in a sensed row	Yes	No
MatrixWriteDistributor<W,K>	Route write data and byte enables to physical columns	Yes	No
StaticReadColumn<R>	Terminal digital primitive sensing one selected ROM/NOR row	Yes	No
MemoryOutputBuffer<W>	Terminal digital primitive publishing data or releasing output as Z	Yes	No

The first three components are gate compositions. StaticReadColumn and MemoryOutputBuffer are terminal digital primitives: they are registered as structural building blocks but directly evaluate their digital contracts, without transistor-level internals or a separate behavioral replacement.

Reuse boundaries

Share a circuit when its signal contract agrees; keep technology-specific sensing and access control separate.

Circuit	Reuse in the implementation	Boundary that remains distinct
Output enable	SRAM's SRAMOutputBuffer<W> is a compatibility wrapper around MemoryOutputBuffer; DRAM/ROM/NOR use the latter directly	The SRAM catalog ID and display name remain unchanged; the wrapper adds no child or delay
Address equality decoding	FF's MemoryAddressDecoder, SRAMRowDecoder, and MatrixRowDecoder share the decodeMatch gate-construction routine	FF supplies range/read-selection signals; SRAM extracts a row from a word address; the matrix decoder accepts a row address
Binary mux trees	FF's MemoryReadSelector and SRAMColumnSelector share the selectMuxTree construction routine	FF selects stored words and pads missing leaves with zero; SRAM selects symbolic bitline pairs and validity before sensing
Post-sense word selection	DRAM/ROM/NOR use MatrixColumnMux; DRAM/NOR also use MatrixWriteDistributor	These operate on ordinary digital bits, not SRAM's complementary bitline interface
Static column sensing	ROM and NOR share StaticReadColumn	SRAM has its own bitline/sense components; DRAM has a destructive-read/restoration sense column

decodeMatch and selectMuxTree in MemoryPeripheralWiring.hpp are C++ construction utilities, not extra simulated components. They build the existing gates in each caller's scope, preserving their names and layout hierarchy. Technology-specific controls, cells, and sensing are not merged. MemoryHelperContractTest checks output timing/X/Z behavior, address interpretation, selection, and boundary geometries; the device contract tests cover their integration.

Configuration

In this page's helper names, R, W, and K describe dimensions; the five common C++ classes themselves take those dimensions as constructor arguments, not template arguments. R is row count, W is bits per word, and K is words per row. The SRAM compatibility wrapper remains a C++ width template.

Use catalog IDs memory.shared.row-decoder, memory.shared.read-column, memory.shared.column-mux.W, memory.shared.write-distributor.W, and memory.shared.output-buffer.W. Row decoder/read column accept runtime rows; mux/distributor accept runtime words_per_row. The output buffer has no configuration parameters beyond the width in its ID. Defaults are R=2 and K=2. Each helper currently has only a structural registration.

The references follow IO pins → behavior → C++ example → implementation → examples → source/tests. C++ examples describe the stated operation; they are not additional registered behavioral implementations. Each example table contains the complete recorded checkpoints and settled times, with an embedded simulation and full-screen link.

3.1.0.1. MatrixRowDecoder<R>

Select one row from a complete 32-bit row index.

IO pins

Pin	Direction	Width	Description
ROW_ADDR	Input	32	Row index, not word or byte address
ENABLE	Input	1	Allow selection
WL_r	Output	1 each	Row enable, 0 ≤ r < R

Behavior

For binary inputs, WL_r = ENABLE AND (ROW_ADDR == r). An invalid address selects no row. All 32 address bits are checked, so high bits cannot alias a valid row. rows=R accepts 1–512.

C++ example

Simplified binary behavior; simulation scheduling and four-state handling are described below.

#include <cstdint>
#include <vector>
std::vector<bool> matrix_decode(unsigned rows, std::uint32_t address, bool enable) {
    std::vector<bool> wl(rows, false);
    if (enable && address < rows) wl[address] = true;
    return wl;
}

Unknown inputs and timing

Gate-level four-state propagation applies. ENABLE=0 forces every WL low even if the address is unknown; otherwise uncertain equality can produce X. Compare after splitter, inversion, and reduction-tree delays settle.

Implementation

Structural implementation

ADDRESS_BITS splits the address. One shared high-bit validation term rejects addresses outside the decoder's low row-index bits; decodeMatch combines that term with each row's low-bit pattern and ENABLE. SRAM and FF use the same construction utility behind their distinct address interfaces. No address truncation or behavioral decoder substitutes for those gates.

Examples

All 10 recorded rows of MatrixRowDecoderTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (3f3be5125c460b70). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	ENABLEInput · 1 bit	ROW_ADDRInput · 32 bit	WL_0Expected output · 1 bit	WL_1Expected output · 1 bit	WL_2Expected output · 1 bit
#0row-0-off	8	0	0x00000000	0	0	0
#1row-0-on	12	1	0x00000000	1	0	0
#2row-1-off	16	0	0x00000001	0	0	0
#3row-1-on	20	1	0x00000001	0	1	0
#4row-2-off	24	0	0x00000002	0	0	0
#5row-2-on	28	1	0x00000002	0	0	1
#6row-3-off	32	0	0x00000003	0	0	0
#7row-3-on	36	1	0x00000003	0	0	0
#8row-4294967295-off	44	0	0xFFFFFFFF	0	0	0
#9row-4294967295-on	46	1	0xFFFFFFFF	0	0	0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Three rows are tested with addresses 0, 1, 2, 3, and 0xFFFFFFFF, each enabled and disabled. All wordlines are checked.

Embedded simulation

The standalone MatrixRowDecoderTest opens this component as MEMORY_ROOT. This component has one registered structural implementation.

Open MatrixRowDecoder<R> in the simulator

Source and tests

• Public interfaces: DigitalMemory.hpp
• Implementation and registration: DigitalMemory.cpp

Test	Coverage
MatrixRowDecoderTest	The complete standalone sequence shown above
MemoryDeviceContractTest	Integration in the new structural devices and comparison with their compact implementations

3.1.0.2. MatrixColumnMux<W,K>

Select a W-bit word from K groups of already sensed columns.

IO pins

Pin	Direction	Width	Description
COLUMN_ADDR	Input	32	Word slot within a row
COL_c	Input	1 each	Sensed bit, 0 ≤ c < W×K
DATA	Output	W	Selected word

Behavior

A valid binary slot selects columns slot*W through slot*W+W−1, in least-significant-bit order. An invalid binary slot produces zero because every selection term is disabled. Device control prevents this zero from masquerading as a successful out-of-range read. K=1 still checks the full slot address.

C++ example

Simplified binary behavior; simulation scheduling and four-state handling are described below.

#include <cstddef>
#include <cstdint>
#include <vector>
std::uint32_t matrix_mux(unsigned width, std::uint32_t slot,
                         const std::vector<bool>& columns) {
    const std::size_t slots = columns.size() / width; // validated W and K
    if (slot >= slots) return 0;
    std::uint32_t word = 0;
    for (unsigned b = 0; b < width; ++b)
        if (columns.at(slot * width + b)) word |= std::uint32_t{1} << b;
    return word;
}

Unknown inputs and timing

AND/OR gate rules determine partial X propagation from unknown slot or selected column bits. This is a logic multiplexer, not a tri-state output buffer. W=8/16/32 and K=1/2/4/8/16; scalar column pins bound its expansion. The decoder and selection trees must settle.

Implementation

Structural implementation

SELECT is a MatrixRowDecoder, held enabled by ENABLED. SELECT_slot_bit gates choose each candidate column; BIT_bit_* OR trees combine candidates. DATA_BITS joins the result into W bits.

Examples

All 4 recorded rows of MatrixColumnMuxTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (3f3be5125c460b70). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	COLUMN_ADDRInput · 32 bit	COL_0Input · 1 bit	COL_1Input · 1 bit	COL_10Input · 1 bit	COL_11Input · 1 bit	COL_12Input · 1 bit	COL_13Input · 1 bit	COL_14Input · 1 bit	COL_15Input · 1 bit	COL_2Input · 1 bit	COL_3Input · 1 bit	COL_4Input · 1 bit	COL_5Input · 1 bit	COL_6Input · 1 bit	COL_7Input · 1 bit	COL_8Input · 1 bit	COL_9Input · 1 bit	DATAExpected output · 8 bit
#0slot-0	11	0x00000000	1	0	1	1	1	1	0	0	1	0	0	1	0	1	0	0	0xA5
#1slot-1	17	0x00000001	1	0	1	1	1	1	0	0	1	0	0	1	0	1	0	0	0x3C
#2slot-2	29	0x00000002	1	0	1	1	1	1	0	0	1	0	0	1	0	1	0	0	0x00
#3slot-4294967295	36	0xFFFFFFFF	1	0	1	1	1	1	0	0	1	0	0	1	0	1	0	0	0x00

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The two groups contain 0xA5 and 0x3C. Slots 0 and 1 select those words; slot 2 and 0xFFFFFFFF return zero.

Embedded simulation

The standalone MatrixColumnMuxTest opens this component as MEMORY_ROOT. This component has one registered structural implementation.

Open MatrixColumnMux<W,K> in the simulator

Source and tests

• Public interfaces: DigitalMemory.hpp
• Implementation and registration: DigitalMemory.cpp

Test	Coverage
MatrixColumnMuxTest	The complete standalone sequence shown above
MemoryDeviceContractTest	Integration in the new structural devices and comparison with their compact implementations

3.1.0.3. MatrixWriteDistributor<W,K>

Fan out write data and qualify each physical column's write enable.

IO pins

Pin	Direction	Width	Description
COLUMN_ADDR	Input	32	Word slot
ENABLE	Input	1	Write/program pulse
DATA	Input	W	Write word
MASK	Input	W/8	One enable per byte, low byte first
DATA_c	Output	1 each	DATA[c%W], 0 ≤ c < W×K
DRIVE_c	Output	1 each	Slot, pulse, and byte-qualified enable

Behavior

DATA is replicated to all K column groups. Only the selected group's enabled byte lanes receive DRIVE. An invalid binary slot selects no drive. Mask bit zero controls bits 0–7 of the selected word. Data fanout itself is not gated; DRIVE determines whether storage uses it.

C++ example

Simplified binary behavior; simulation scheduling and four-state handling are described below.

#include <array>
#include <cstdint>
std::array<bool, 2> matrix_write_column(unsigned width, unsigned column,
                                      std::uint32_t slot, bool enable,
                                      std::uint32_t data, unsigned mask) {
    const unsigned bit = column % width;
    const bool drive = enable && slot == column / width &&
                       ((mask >> (bit / 8)) & 1u);
    return {bool((data >> bit) & 1u), drive}; // DATA_c, DRIVE_c
}

Unknown inputs and timing

A known disabled enable or masked-off lane forces drive low even with uncertain other controls. Unknown enabled masks/addresses propagate through the gates. Data X/Z is copied; the receiving cell decides its storage meaning. W/K have the same bounds as MatrixColumnMux.

Implementation

Structural implementation

SELECT decodes slot and ENABLE. DATA_BITS splits W data bits. Wider words use MASK_BITS; W=8 connects its one-bit mask directly, without a width-one splitter. One WRITE_slot_byte gate qualifies each selected byte and fans out to its eight physical columns.

Examples

All 7 recorded rows of MatrixWriteDistributorTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (3f3be5125c460b70). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	COLUMN_ADDRInput · 32 bit	DATAInput · 8 bit	ENABLEInput · 1 bit	MASKInput · 1 bit	DATA_0Expected output · 1 bit	DATA_1Expected output · 1 bit	DATA_10Expected output · 1 bit	DATA_11Expected output · 1 bit	DATA_12Expected output · 1 bit	DATA_13Expected output · 1 bit	DATA_14Expected output · 1 bit	DATA_15Expected output · 1 bit	DATA_2Expected output · 1 bit	DATA_3Expected output · 1 bit	DATA_4Expected output · 1 bit	DATA_5Expected output · 1 bit	DATA_6Expected output · 1 bit	DATA_7Expected output · 1 bit	DATA_8Expected output · 1 bit	DATA_9Expected output · 1 bit	DRIVE_0Expected output · 1 bit	DRIVE_1Expected output · 1 bit	DRIVE_10Expected output · 1 bit	DRIVE_11Expected output · 1 bit	DRIVE_12Expected output · 1 bit	DRIVE_13Expected output · 1 bit	DRIVE_14Expected output · 1 bit	DRIVE_15Expected output · 1 bit	DRIVE_2Expected output · 1 bit	DRIVE_3Expected output · 1 bit	DRIVE_4Expected output · 1 bit	DRIVE_5Expected output · 1 bit	DRIVE_6Expected output · 1 bit	DRIVE_7Expected output · 1 bit	DRIVE_8Expected output · 1 bit	DRIVE_9Expected output · 1 bit
#0slot-0-off	8	0x00000000	0xA5	0	1	1	0	1	0	0	1	0	1	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#1slot-0-on	12	0x00000000	0xA5	1	1	1	0	1	0	0	1	0	1	1	0	0	1	0	1	1	0	1	1	0	0	0	0	0	0	1	1	1	1	1	1	0	0
#2slot-1-off	16	0x00000001	0xA5	0	1	1	0	1	0	0	1	0	1	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#3slot-1-on	20	0x00000001	0xA5	1	1	1	0	1	0	0	1	0	1	1	0	0	1	0	1	1	0	0	0	1	1	1	1	1	1	0	0	0	0	0	0	1	1
#4slot-2-off	29	0x00000002	0xA5	0	1	1	0	1	0	0	1	0	1	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#5slot-2-on	31	0x00000002	0xA5	1	1	1	0	1	0	0	1	0	1	1	0	0	1	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
#6masked	42	0x00000000	0xA5	1	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	0	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Tests slots 0, 1, and invalid 2 with ENABLE low/high, checks data fanout and every drive, then disables the byte mask.

Embedded simulation

The standalone MatrixWriteDistributorTest opens this component as MEMORY_ROOT. This component has one registered structural implementation.

Open MatrixWriteDistributor<W,K> in the simulator

Source and tests

• Public interfaces: DigitalMemory.hpp
• Implementation and registration: DigitalMemory.cpp

Test	Coverage
MatrixWriteDistributorTest	The complete standalone sequence shown above
MemoryDeviceContractTest	Integration in the new structural devices and comparison with their compact implementations

3.1.0.4. StaticReadColumn<R>

Digitally sense one column from exactly one selected ROM/flash row.

IO pins

Pin	Direction	Width	Description
WL_r	Input	1 each	Row selection, 0 ≤ r < R
Q_r	Input	1 each	Stored bit in row r
OUT	Output	1	Selected stored bit, otherwise X

Behavior

All wordlines must be binary and exactly one must be high. OUT then reproduces that row's bit; no selection or multiple selection returns X. This component has no stored row buffer or destructive-read behavior. DRAM uses its own sense column.

C++ example

Binary wordlines with optional stored bits. Empty output means X.

#include <optional>
#include <vector>
std::optional<bool> static_read_column(const std::vector<bool>& wl,
                                       const std::vector<std::optional<bool>>& q) {
    unsigned selected = 0;
    std::optional<bool> out;
    for (unsigned r = 0; r < wl.size(); ++r) {
        if (!wl[r]) continue;
        ++selected;
        out = q.at(r);
    }
    return selected == 1 ? out : std::nullopt;
}

Unknown inputs and timing

Any unknown wordline makes OUT=X, even if another row is known selected. Selected Q=X or Z produces X; unselected Q values do not matter. rows accepts 1–512. The primitive publishes after one tick.

Implementation

Structural implementation

Terminal digital selected-row sensing primitive. Its inputs represent cell states and wordlines; it does not simulate an analog shared bitline or multi-driver voltage resolution.

Examples

All 5 recorded rows of StaticReadColumnTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (3f3be5125c460b70). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	Q_0Input · 1 bit	Q_1Input · 1 bit	WL_0Input · 1 bit	WL_1Input · 1 bit	OUTExpected output · 1 bit
#0none	1	0	1	0	0	X
#1row-zero	3	0	1	1	0	0
#2conflict	5	0	1	1	1	X
#3row-one	7	0	1	0	1	1
#4unknown-select	9	0	1	X	1	X

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Checks no selection, row zero, conflicting rows, row one, and an unknown row select.

Embedded simulation

The standalone StaticReadColumnTest opens this component as MEMORY_ROOT. This component has one registered structural implementation.

Open StaticReadColumn<R> in the simulator

Source and tests

• Public interfaces: DigitalMemory.hpp
• Implementation and registration: DigitalMemory.cpp

Test	Coverage
StaticReadColumnTest	The complete standalone sequence shown above
MemoryDeviceContractTest	Integration in the new structural devices and comparison with their compact implementations

3.1.0.5. MemoryOutputBuffer<W>

Publish a word or release the output as high impedance.

IO pins

Pin	Direction	Width	Description
DATA	Input	W	Candidate output word
ENABLE	Input	1	Output enable
OUT	Output	W	DATA, Z, or X

Behavior

ENABLE=1 copies DATA unchanged; ENABLE=0 emits all Z; ENABLE=X or Z emits all X. The buffer does not validate an address or store data.

C++ example

Binary enable with an explicit released result. The simulator also supports X/Z values per bit.

#include <cstdint>
#include <optional>
std::optional<std::uint32_t> memory_output(std::uint32_t data, bool enable) {
    return enable ? std::optional(data) : std::nullopt; // nullopt denotes Z here
}

Unknown inputs and timing

Enabled data preserves every bit, including X or Z. Unknown enable produces all X rather than guessing data or release. W=8/16/32. Output delay is one primitive tick; this does not make the engine an electrical multi-driver bus simulator.

Implementation

Structural implementation

Terminal digital output-enable primitive. Device control drives ENABLE; the word selector drives DATA. SRAMOutputBuffer<W> inherits this same implementation while preserving its existing SRAM-facing identity; DRAM/ROM/NOR instantiate it directly. No separate behavioral replacement is registered.

Examples

All 4 recorded rows of MemoryOutputBufferTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (3f3be5125c460b70). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	DATAInput · 8 bit	ENABLEInput · 1 bit	OUTExpected output · 8 bit
#0enable-0	1	0xA5	0	0bZZZZZZZZ
#1enable-1	3	0xA5	1	0xA5
#2enable-2	5	0xA5	X	0bXXXXXXXX
#3enable-3	6	0xA5	Z	0bXXXXXXXX

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Uses DATA=0xA5 with ENABLE=0, 1, X, and Z, checking all output bits at each checkpoint.

Embedded simulation

The standalone MemoryOutputBufferTest opens this component as MEMORY_ROOT. This component has one registered structural implementation.

Open MemoryOutputBuffer<W> in the simulator

Source and tests

• Public interfaces: DigitalMemory.hpp
• Implementation and registration: DigitalMemory.cpp

Test	Coverage
MemoryOutputBufferTest	The complete standalone sequence shown above
MemoryDeviceContractTest	Integration in the new structural devices and comparison with their compact implementations