§ 4.3.3. ALU32

ALU32 is the complete combinational arithmetic/logic reference. RV32I Execute uses its ALU32Core variant: the same arithmetic, logic, shifting, and comparison network without the result-flag outputs that Execute never reads. Its five-bit operation encoding is not the ALU8 encoding. There is no carry input, multiplication, division, rotation, or invalid-operation output.

The single-cycle Execute stage has one instance at CORE.EXECUTE.ALU, shared by arithmetic, address calculation, branch comparison, and JAL/JALR target calculation. PC+4 and the concurrent branch-target addition use separate adders; Writeback supplies jump links.

Component	Description	Structural	Behavioral
AddSub32	Shared addition/subtraction with carry and overflow	Yes	Yes
Logic32	Parallel AND, OR, and XOR	Yes	Yes
Shifter32	Logical left/right and arithmetic right shifts	Yes	Yes
ALU32ControlDecoder	Opcode split and local controls	Yes	No
ALU32CompareUnit	Comparison flags and Boolean result words from subtraction	Yes	No
ALU32ResultSelector	Selects the operation result	Yes	No
ALU32FlagUnit	Result flags and arithmetic-flag qualification	Yes	No
ALU32	Complete unit with the RV32I ALU interface	Yes	Yes
ALU32Core	CPU datapath variant with result and branch-comparison outputs	Yes	Yes

Columns describe registered simulator implementations, not the C++ examples. The examples describe settled binary behavior, omit delays and X/Z, and can be compiled together in page order. Arithmetic uses unsigned 32-bit words and wraps modulo \(2^{32}\).

4.3.3.1. AddSub32

IO pins

Pin	Direction	Width	Description
A, B	Input	32 each	Operands
SUB	Input	1	0: addition; 1: subtraction
OUT	Output	32	Wrapped result
CARRY_OUT	Output	1	Addition carry; subtraction no borrow
OVERFLOW	Output	1	Signed overflow

Behavior

The shared adder computes A + (B XOR {32{SUB}}) + SUB. Subtraction therefore sets carry when unsigned A >= B. Overflow is independent of unsigned carry.

C++ example

#include <array>
#include <cstdint>
namespace alu32_example {
struct Arithmetic { uint32_t OUT; bool CARRY_OUT, OVERFLOW; };
Arithmetic addsub(uint32_t a, uint32_t b, bool sub) {
    const uint64_t wide = uint64_t(a) + (sub ? ~b : b) + sub;
    const uint32_t out = uint32_t(wide);
    const bool overflow = ((sub ? (a ^ b) : ~(a ^ b)) & (a ^ out) & 0x80000000U) != 0;
    return {out, bool(wide >> 32), overflow};
}
}

Unknown inputs and timing

Each bit follows XOR/AND/OR full-adder logic. A known controlling zero or one can mask an unknown; the entire word is not automatically discarded. Structural carries propagate through a prefix network. The catalog-selected behavioral implementation uses gate-derived path delays; a supported delay twin can time how far the carry propagates for the current operands.

Implementation

Structural implementation

Each B bit passes through an XOR with SUB; SUB also supplies carry-in to the shared prefix adder. A joiner collects sums. XOR of the carry into and out of bit 31 produces overflow. The optional ripple reference instead uses 32 chained FullAdder stages.

The default structural implementation uses ParallelPrefixAdder32: HalfAdder bit generate/propagate signals, five grouped carry-prefix levels (distances 1, 2, 4, 8, 16), then carry-in application and sum XORs. CarryCombine contains only AND/OR gates. Overflow remains carry into bit 31 XOR carry out. Adder32 uses the same prefix component, so all cores receive the arithmetic improvement. The original ripple structure remains constructible with Component::create<AddSub32>("RIPPLE", false) (and likewise Adder32) for comparison.

The default layout follows connectivity. Prefix levels are expandable groups rather than one flat gate diagram. ArithmeticTimingOptimizationTest compares both structures on binary and four-state inputs; the five-level carry network changes propagation time, not the settled arithmetic contract.

Behavioral implementation

AddSub32Behavioral evaluates that same full-adder recurrence with four-state bit values, without constructing its internal gates.

Examples

All 80 recorded rows of AddSub32Test, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (16dc1c073540b939). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	AInput · 32 bit	BInput · 32 bit	SUBInput · 1 bit	CARRY_OUTExpected output · 1 bit	OUTExpected output · 32 bit	OVERFLOWExpected output · 1 bit
#0row-0	18	0x00000000	0x00000000	0	0	0x00000000	0
#1row-1	31	0x00000001	0x00000002	0	0	0x00000003	0
#2row-2	54	0xFFFFFFFF	0x00000001	0	1	0x00000000	0
#3row-3	70	0xFFFFFFFF	0xFFFFFFFF	0	1	0xFFFFFFFE	0
#4row-4	93	0x55555555	0xAAAAAAAA	0	0	0xFFFFFFFF	0
#5row-5	111	0x55555555	0xAAAAAAAA	1	0	0xAAAAAAAB	1
#6row-6	132	0x7FFFFFFF	0x00000001	0	0	0x80000000	1
#7row-7	150	0x80000000	0x80000000	0	1	0x00000000	1
#8row-8	169	0x7FFFFFFF	0xFFFFFFFF	0	1	0x7FFFFFFE	0
#9row-9	191	0x00000005	0x00000003	1	1	0x00000002	0
#10row-10	211	0x00000000	0x00000001	1	0	0xFFFFFFFF	0
#11row-11	227	0x80000000	0x00000001	1	1	0x7FFFFFFF	1
#12row-12	246	0x7FFFFFFF	0xFFFFFFFF	1	0	0x80000000	1
#13row-13	264	0x80000000	0x7FFFFFFF	1	1	0x00000001	1
#14row-14	283	0xFFFFFFFF	0xFFFFFFFF	1	1	0x00000000	0
#15row-15	302	0x00000001	0x00000001	0	0	0x00000002	0
#16row-16	323	0x00000002	0x00000001	1	1	0x00000001	0
#17row-17	341	0x00000003	0x00000001	0	0	0x00000004	0
#18row-18	362	0x00000004	0x00000001	1	1	0x00000003	0
#19row-19	380	0x00000007	0x00000001	0	0	0x00000008	0
#20row-20	401	0x00000008	0x00000001	1	1	0x00000007	0
#21row-21	419	0x0000000F	0x00000001	0	0	0x00000010	0
#22row-22	440	0x00000010	0x00000001	1	1	0x0000000F	0
#23row-23	458	0x0000001F	0x00000001	0	0	0x00000020	0
#24row-24	479	0x00000020	0x00000001	1	1	0x0000001F	0
#25row-25	497	0x0000003F	0x00000001	0	0	0x00000040	0
#26row-26	518	0x00000040	0x00000001	1	1	0x0000003F	0
#27row-27	536	0x0000007F	0x00000001	0	0	0x00000080	0
#28row-28	557	0x00000080	0x00000001	1	1	0x0000007F	0
#29row-29	575	0x000000FF	0x00000001	0	0	0x00000100	0
#30row-30	596	0x00000100	0x00000001	1	1	0x000000FF	0
#31row-31	614	0x000001FF	0x00000001	0	0	0x00000200	0
#32row-32	635	0x00000200	0x00000001	1	1	0x000001FF	0
#33row-33	653	0x000003FF	0x00000001	0	0	0x00000400	0
#34row-34	674	0x00000400	0x00000001	1	1	0x000003FF	0
#35row-35	692	0x000007FF	0x00000001	0	0	0x00000800	0
#36row-36	713	0x00000800	0x00000001	1	1	0x000007FF	0
#37row-37	731	0x00000FFF	0x00000001	0	0	0x00001000	0
#38row-38	752	0x00001000	0x00000001	1	1	0x00000FFF	0
#39row-39	770	0x00001FFF	0x00000001	0	0	0x00002000	0
#40row-40	791	0x00002000	0x00000001	1	1	0x00001FFF	0
#41row-41	809	0x00003FFF	0x00000001	0	0	0x00004000	0
#42row-42	830	0x00004000	0x00000001	1	1	0x00003FFF	0
#43row-43	849	0x00007FFF	0x00000001	0	0	0x00008000	0
#44row-44	870	0x00008000	0x00000001	1	1	0x00007FFF	0
#45row-45	890	0x0000FFFF	0x00000001	0	0	0x00010000	0
#46row-46	911	0x00010000	0x00000001	1	1	0x0000FFFF	0
#47row-47	931	0x0001FFFF	0x00000001	0	0	0x00020000	0
#48row-48	951	0x00020000	0x00000001	1	1	0x0001FFFF	0
#49row-49	971	0x0003FFFF	0x00000001	0	0	0x00040000	0
#50row-50	991	0x00040000	0x00000001	1	1	0x0003FFFF	0
#51row-51	1011	0x0007FFFF	0x00000001	0	0	0x00080000	0
#52row-52	1031	0x00080000	0x00000001	1	1	0x0007FFFF	0
#53row-53	1051	0x000FFFFF	0x00000001	0	0	0x00100000	0
#54row-54	1071	0x00100000	0x00000001	1	1	0x000FFFFF	0
#55row-55	1091	0x001FFFFF	0x00000001	0	0	0x00200000	0
#56row-56	1111	0x00200000	0x00000001	1	1	0x001FFFFF	0
#57row-57	1131	0x003FFFFF	0x00000001	0	0	0x00400000	0
#58row-58	1151	0x00400000	0x00000001	1	1	0x003FFFFF	0
#59row-59	1171	0x007FFFFF	0x00000001	0	0	0x00800000	0
#60row-60	1191	0x00800000	0x00000001	1	1	0x007FFFFF	0
#61row-61	1211	0x00FFFFFF	0x00000001	0	0	0x01000000	0
#62row-62	1231	0x01000000	0x00000001	1	1	0x00FFFFFF	0
#63row-63	1251	0x01FFFFFF	0x00000001	0	0	0x02000000	0
#64row-64	1270	0x02000000	0x00000001	1	1	0x01FFFFFF	0
#65row-65	1290	0x03FFFFFF	0x00000001	0	0	0x04000000	0
#66row-66	1309	0x04000000	0x00000001	1	1	0x03FFFFFF	0
#67row-67	1329	0x07FFFFFF	0x00000001	0	0	0x08000000	0
#68row-68	1348	0x08000000	0x00000001	1	1	0x07FFFFFF	0
#69row-69	1368	0x0FFFFFFF	0x00000001	0	0	0x10000000	0
#70row-70	1387	0x10000000	0x00000001	1	1	0x0FFFFFFF	0
#71row-71	1407	0x1FFFFFFF	0x00000001	0	0	0x20000000	0
#72row-72	1425	0x20000000	0x00000001	1	1	0x1FFFFFFF	0
#73row-73	1445	0x3FFFFFFF	0x00000001	0	0	0x40000000	0
#74row-74	1463	0x40000000	0x00000001	1	1	0x3FFFFFFF	0
#75row-75	1484	0x7FFFFFFF	0x00000001	0	0	0x80000000	1
#76row-76	1501	0x80000000	0x00000001	1	1	0x7FFFFFFF	1
#77row-77	1519	0b00000000000000000000000000X00000	0x00000000	0	0	0b00000000000000000000000000X00000	0
#78row-78	1522	0b00000000000000000000000000Z00000	0x00000000	0	0	0b00000000000000000000000000X00000	0
#79row-79	1540	0x00000000	0x00000000	X	X	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	X

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open AddSub32

Tests

AddSub32Test checks arithmetic boundaries and flags in both implementations. The table contains every checkpoint of the displayed scenario, with its recorded time.

4.3.3.2. Logic32

IO pins

Pin	Direction	Width	Description
A, B	Input	32 each	Operands
AND_OUT, OR_OUT, XOR_OUT	Output	32 each	Three simultaneous bitwise results

Behavior

All three outputs are active together; there is no opcode or enable.

C++ example

namespace alu32_example {
struct Logic { uint32_t AND_OUT, OR_OUT, XOR_OUT; };
Logic logic(uint32_t a, uint32_t b) { return {a & b, a | b, a ^ b}; }
}

Unknown inputs and timing

AND with zero produces zero; OR with one produces one. Other indeterminate cases produce X, including XOR with X or Z. Operations are independent per bit.

Implementation

Structural implementation

Two splitters, 32 gates of each operation, and three joiners provide three parallel paths.

Behavioral implementation

Logic32Behavioral applies the same four-state gate rules per bit and publishes when the gate-level form would have settled for the same inputs.

Examples

All 69 recorded rows of Logic32Test, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (6c28b35478130092). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	AInput · 32 bit	BInput · 32 bit	AND_OUTExpected output · 32 bit	OR_OUTExpected output · 32 bit	XOR_OUTExpected output · 32 bit
#0row-0	2	0xF0F0F0F0	0x0FF00FF0	0x00F000F0	0xFFF0FFF0	0xFF00FF00
#1row-1	5	0xFFFFFFFF	0x00000000	0x00000000	0xFFFFFFFF	0xFFFFFFFF
#2row-2	8	0xAAAAAAAA	0x55555555	0x00000000	0xFFFFFFFF	0xFFFFFFFF
#3row-3	11	0x80000000	0x7FFFFFFF	0x00000000	0xFFFFFFFF	0xFFFFFFFF
#4row-4	14	0x00000001	0x00000000	0x00000000	0x00000001	0x00000001
#5row-5	17	0x00000001	0x00000001	0x00000001	0x00000001	0x00000000
#6row-6	20	0x00000002	0x00000000	0x00000000	0x00000002	0x00000002
#7row-7	23	0x00000002	0x00000002	0x00000002	0x00000002	0x00000000
#8row-8	26	0x00000004	0x00000000	0x00000000	0x00000004	0x00000004
#9row-9	29	0x00000004	0x00000004	0x00000004	0x00000004	0x00000000
#10row-10	32	0x00000008	0x00000000	0x00000000	0x00000008	0x00000008
#11row-11	35	0x00000008	0x00000008	0x00000008	0x00000008	0x00000000
#12row-12	38	0x00000010	0x00000000	0x00000000	0x00000010	0x00000010
#13row-13	41	0x00000010	0x00000010	0x00000010	0x00000010	0x00000000
#14row-14	44	0x00000020	0x00000000	0x00000000	0x00000020	0x00000020
#15row-15	47	0x00000020	0x00000020	0x00000020	0x00000020	0x00000000
#16row-16	50	0x00000040	0x00000000	0x00000000	0x00000040	0x00000040
#17row-17	53	0x00000040	0x00000040	0x00000040	0x00000040	0x00000000
#18row-18	56	0x00000080	0x00000000	0x00000000	0x00000080	0x00000080
#19row-19	59	0x00000080	0x00000080	0x00000080	0x00000080	0x00000000
#20row-20	62	0x00000100	0x00000000	0x00000000	0x00000100	0x00000100
#21row-21	65	0x00000100	0x00000100	0x00000100	0x00000100	0x00000000
#22row-22	68	0x00000200	0x00000000	0x00000000	0x00000200	0x00000200
#23row-23	71	0x00000200	0x00000200	0x00000200	0x00000200	0x00000000
#24row-24	74	0x00000400	0x00000000	0x00000000	0x00000400	0x00000400
#25row-25	77	0x00000400	0x00000400	0x00000400	0x00000400	0x00000000
#26row-26	80	0x00000800	0x00000000	0x00000000	0x00000800	0x00000800
#27row-27	83	0x00000800	0x00000800	0x00000800	0x00000800	0x00000000
#28row-28	86	0x00001000	0x00000000	0x00000000	0x00001000	0x00001000
#29row-29	89	0x00001000	0x00001000	0x00001000	0x00001000	0x00000000
#30row-30	92	0x00002000	0x00000000	0x00000000	0x00002000	0x00002000
#31row-31	95	0x00002000	0x00002000	0x00002000	0x00002000	0x00000000
#32row-32	98	0x00004000	0x00000000	0x00000000	0x00004000	0x00004000
#33row-33	101	0x00004000	0x00004000	0x00004000	0x00004000	0x00000000
#34row-34	104	0x00008000	0x00000000	0x00000000	0x00008000	0x00008000
#35row-35	107	0x00008000	0x00008000	0x00008000	0x00008000	0x00000000
#36row-36	110	0x00010000	0x00000000	0x00000000	0x00010000	0x00010000
#37row-37	113	0x00010000	0x00010000	0x00010000	0x00010000	0x00000000
#38row-38	116	0x00020000	0x00000000	0x00000000	0x00020000	0x00020000
#39row-39	119	0x00020000	0x00020000	0x00020000	0x00020000	0x00000000
#40row-40	122	0x00040000	0x00000000	0x00000000	0x00040000	0x00040000
#41row-41	125	0x00040000	0x00040000	0x00040000	0x00040000	0x00000000
#42row-42	128	0x00080000	0x00000000	0x00000000	0x00080000	0x00080000
#43row-43	131	0x00080000	0x00080000	0x00080000	0x00080000	0x00000000
#44row-44	134	0x00100000	0x00000000	0x00000000	0x00100000	0x00100000
#45row-45	137	0x00100000	0x00100000	0x00100000	0x00100000	0x00000000
#46row-46	140	0x00200000	0x00000000	0x00000000	0x00200000	0x00200000
#47row-47	143	0x00200000	0x00200000	0x00200000	0x00200000	0x00000000
#48row-48	146	0x00400000	0x00000000	0x00000000	0x00400000	0x00400000
#49row-49	149	0x00400000	0x00400000	0x00400000	0x00400000	0x00000000
#50row-50	152	0x00800000	0x00000000	0x00000000	0x00800000	0x00800000
#51row-51	155	0x00800000	0x00800000	0x00800000	0x00800000	0x00000000
#52row-52	158	0x01000000	0x00000000	0x00000000	0x01000000	0x01000000
#53row-53	161	0x01000000	0x01000000	0x01000000	0x01000000	0x00000000
#54row-54	164	0x02000000	0x00000000	0x00000000	0x02000000	0x02000000
#55row-55	167	0x02000000	0x02000000	0x02000000	0x02000000	0x00000000
#56row-56	170	0x04000000	0x00000000	0x00000000	0x04000000	0x04000000
#57row-57	173	0x04000000	0x04000000	0x04000000	0x04000000	0x00000000
#58row-58	176	0x08000000	0x00000000	0x00000000	0x08000000	0x08000000
#59row-59	179	0x08000000	0x08000000	0x08000000	0x08000000	0x00000000
#60row-60	182	0x10000000	0x00000000	0x00000000	0x10000000	0x10000000
#61row-61	185	0x10000000	0x10000000	0x10000000	0x10000000	0x00000000
#62row-62	188	0x20000000	0x00000000	0x00000000	0x20000000	0x20000000
#63row-63	191	0x20000000	0x20000000	0x20000000	0x20000000	0x00000000
#64row-64	194	0x40000000	0x00000000	0x00000000	0x40000000	0x40000000
#65row-65	197	0x40000000	0x40000000	0x40000000	0x40000000	0x00000000
#66row-66	200	0x80000000	0x00000000	0x00000000	0x80000000	0x80000000
#67row-67	203	0x80000000	0x80000000	0x80000000	0x80000000	0x00000000
#68row-68	206	0bZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10	0b10ZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX	0bX0X0X0X0X0X0X0X0X0X0X0X0X0X0X0X0	0b1X1X1X1X1X1X1X1X1X1X1X1X1X1X1X1X	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open Logic32

Tests

Logic32Test checks all three outputs and selected four-state cases against both implementations.

4.3.3.3. Shifter32

IO pins

Pin	Direction	Width	Description
A	Input	32	Word being shifted
B	Input	32	Shift amount is only B[4:0]
LEFT	Input	1	1: left; 0: right
ARITHMETIC	Input	1	Sign-fill for right shifts; ignored for left shifts
OUT	Output	32	Shifted word

Behavior

Shift distance is 0–31. Left shifts and logical right shifts fill with zero; arithmetic right shifts fill with the original sign bit. A distance of zero preserves the word. There is no shifted-out carry output.

C++ example

namespace alu32_example {
uint32_t shift(uint32_t a, uint32_t b, bool left, bool arithmetic) {
    const unsigned n = b & 31;
    if (left) return a << n;
    uint32_t out = a >> n;
    if (n && arithmetic && (a & 0x80000000U)) out |= ~uint32_t{0} << (32 - n);
    return out;
}
}

Unknown inputs and timing

B[31:5] are unused, even when unknown. The remaining bits follow the gate-based mux network; an unknown selector does not necessarily preserve equal one-valued mux inputs. Left shifting disables sign fill. The structural path includes five selectable shift stages.

Implementation

Structural implementation

A shared right-shift network selects distances 1, 2, 4, 8, and 16. Input/output reversal muxes reuse it for left shifts. Fill is A[31] AND ARITHMETIC AND NOT LEFT.

Behavioral implementation

Shifter32Behavioral reproduces the reversal, each mux stage, and fill logic using four-state values. Catalog construction gives it gate-derived output delays, with a delay twin where supported to time the current shift and data.

Examples

All 447 recorded rows of Shifter32Test, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (62729ffe071d2eb3). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	AInput · 32 bit	ARITHMETICInput · 1 bit	BInput · 32 bit	LEFTInput · 1 bit	OUTExpected output · 32 bit
#0row-0	15	0x80000001	0	0x00000000	1	0x80000001
#1row-1	31	0x80000001	0	0x00000000	0	0x80000001
#2row-2	35	0x80000001	1	0x00000000	0	0x80000001
#3row-3	51	0x7FFFFFFF	0	0x00000000	1	0x7FFFFFFF
#4row-4	67	0x7FFFFFFF	0	0x00000000	0	0x7FFFFFFF
#5row-5	69	0x7FFFFFFF	1	0x00000000	0	0x7FFFFFFF
#6row-6	84	0xFFFFFFFF	0	0x00000000	1	0xFFFFFFFF
#7row-7	100	0xFFFFFFFF	0	0x00000000	0	0xFFFFFFFF
#8row-8	104	0xFFFFFFFF	1	0x00000000	0	0xFFFFFFFF
#9row-9	120	0x00000001	0	0x00000000	1	0x00000001
#10row-10	136	0x00000001	0	0x00000000	0	0x00000001
#11row-11	138	0x00000001	1	0x00000000	0	0x00000001
#12row-12	153	0x80000001	0	0x00000001	1	0x00000002
#13row-13	169	0x80000001	0	0x00000001	0	0x40000000
#14row-14	184	0x80000001	1	0x00000001	0	0xC0000000
#15row-15	200	0x7FFFFFFF	0	0x00000001	1	0xFFFFFFFE
#16row-16	216	0x7FFFFFFF	0	0x00000001	0	0x3FFFFFFF
#17row-17	218	0x7FFFFFFF	1	0x00000001	0	0x3FFFFFFF
#18row-18	233	0xFFFFFFFF	0	0x00000001	1	0xFFFFFFFE
#19row-19	249	0xFFFFFFFF	0	0x00000001	0	0x7FFFFFFF
#20row-20	264	0xFFFFFFFF	1	0x00000001	0	0xFFFFFFFF
#21row-21	280	0x00000001	0	0x00000001	1	0x00000002
#22row-22	295	0x00000001	0	0x00000001	0	0x00000000
#23row-23	297	0x00000001	1	0x00000001	0	0x00000000
#24row-24	312	0x80000001	0	0x00000002	1	0x00000004
#25row-25	328	0x80000001	0	0x00000002	0	0x20000000
#26row-26	341	0x80000001	1	0x00000002	0	0xE0000000
#27row-27	357	0x7FFFFFFF	0	0x00000002	1	0xFFFFFFFC
#28row-28	373	0x7FFFFFFF	0	0x00000002	0	0x1FFFFFFF
#29row-29	375	0x7FFFFFFF	1	0x00000002	0	0x1FFFFFFF
#30row-30	390	0xFFFFFFFF	0	0x00000002	1	0xFFFFFFFC
#31row-31	406	0xFFFFFFFF	0	0x00000002	0	0x3FFFFFFF
#32row-32	419	0xFFFFFFFF	1	0x00000002	0	0xFFFFFFFF
#33row-33	435	0x00000001	0	0x00000002	1	0x00000004
#34row-34	450	0x00000001	0	0x00000002	0	0x00000000
#35row-35	452	0x00000001	1	0x00000002	0	0x00000000
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#318row-318	4118	0xFFFFFFFF	0	0x0000001A	1	0xFC000000
#319row-319	4134	0xFFFFFFFF	0	0x0000001A	0	0x0000003F
#320row-320	4147	0xFFFFFFFF	1	0x0000001A	0	0xFFFFFFFF
#321row-321	4163	0x00000001	0	0x0000001A	1	0x04000000
#322row-322	4178	0x00000001	0	0x0000001A	0	0x00000000
#323row-323	4180	0x00000001	1	0x0000001A	0	0x00000000
#324row-324	4195	0x80000001	0	0x0000001B	1	0x08000000
#325row-325	4211	0x80000001	0	0x0000001B	0	0x00000010
#326row-326	4226	0x80000001	1	0x0000001B	0	0xFFFFFFF0
#327row-327	4242	0x7FFFFFFF	0	0x0000001B	1	0xF8000000
#328row-328	4258	0x7FFFFFFF	0	0x0000001B	0	0x0000000F
#329row-329	4260	0x7FFFFFFF	1	0x0000001B	0	0x0000000F
#330row-330	4275	0xFFFFFFFF	0	0x0000001B	1	0xF8000000
#331row-331	4291	0xFFFFFFFF	0	0x0000001B	0	0x0000001F
#332row-332	4306	0xFFFFFFFF	1	0x0000001B	0	0xFFFFFFFF
#333row-333	4322	0x00000001	0	0x0000001B	1	0x08000000
#334row-334	4337	0x00000001	0	0x0000001B	0	0x00000000
#335row-335	4339	0x00000001	1	0x0000001B	0	0x00000000
#336row-336	4354	0x80000001	0	0x0000001C	1	0x10000000
#337row-337	4370	0x80000001	0	0x0000001C	0	0x00000008
#338row-338	4381	0x80000001	1	0x0000001C	0	0xFFFFFFF8
#339row-339	4397	0x7FFFFFFF	0	0x0000001C	1	0xF0000000
#340row-340	4413	0x7FFFFFFF	0	0x0000001C	0	0x00000007
#341row-341	4415	0x7FFFFFFF	1	0x0000001C	0	0x00000007
#342row-342	4430	0xFFFFFFFF	0	0x0000001C	1	0xF0000000
#343row-343	4446	0xFFFFFFFF	0	0x0000001C	0	0x0000000F
#344row-344	4457	0xFFFFFFFF	1	0x0000001C	0	0xFFFFFFFF
#345row-345	4473	0x00000001	0	0x0000001C	1	0x10000000
#346row-346	4488	0x00000001	0	0x0000001C	0	0x00000000
#347row-347	4490	0x00000001	1	0x0000001C	0	0x00000000
#348row-348	4505	0x80000001	0	0x0000001D	1	0x20000000
#349row-349	4521	0x80000001	0	0x0000001D	0	0x00000004
#350row-350	4536	0x80000001	1	0x0000001D	0	0xFFFFFFFC
#351row-351	4552	0x7FFFFFFF	0	0x0000001D	1	0xE0000000
#352row-352	4568	0x7FFFFFFF	0	0x0000001D	0	0x00000003
#353row-353	4570	0x7FFFFFFF	1	0x0000001D	0	0x00000003
#354row-354	4585	0xFFFFFFFF	0	0x0000001D	1	0xE0000000
#355row-355	4601	0xFFFFFFFF	0	0x0000001D	0	0x00000007
#356row-356	4616	0xFFFFFFFF	1	0x0000001D	0	0xFFFFFFFF
#357row-357	4632	0x00000001	0	0x0000001D	1	0x20000000
#358row-358	4647	0x00000001	0	0x0000001D	0	0x00000000
#359row-359	4649	0x00000001	1	0x0000001D	0	0x00000000
#360row-360	4664	0x80000001	0	0x0000001E	1	0x40000000
#361row-361	4680	0x80000001	0	0x0000001E	0	0x00000002
#362row-362	4693	0x80000001	1	0x0000001E	0	0xFFFFFFFE
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#364row-364	4725	0x7FFFFFFF	0	0x0000001E	0	0x00000001
#365row-365	4727	0x7FFFFFFF	1	0x0000001E	0	0x00000001
#366row-366	4742	0xFFFFFFFF	0	0x0000001E	1	0xC0000000
#367row-367	4758	0xFFFFFFFF	0	0x0000001E	0	0x00000003
#368row-368	4771	0xFFFFFFFF	1	0x0000001E	0	0xFFFFFFFF
#369row-369	4787	0x00000001	0	0x0000001E	1	0x40000000
#370row-370	4802	0x00000001	0	0x0000001E	0	0x00000000
#371row-371	4804	0x00000001	1	0x0000001E	0	0x00000000
#372row-372	4819	0x80000001	0	0x0000001F	1	0x80000000
#373row-373	4835	0x80000001	0	0x0000001F	0	0x00000001
#374row-374	4850	0x80000001	1	0x0000001F	0	0xFFFFFFFF
#375row-375	4865	0x7FFFFFFF	0	0x0000001F	1	0x80000000
#376row-376	4880	0x7FFFFFFF	0	0x0000001F	0	0x00000000
#377row-377	4882	0x7FFFFFFF	1	0x0000001F	0	0x00000000
#378row-378	4897	0xFFFFFFFF	0	0x0000001F	1	0x80000000
#379row-379	4913	0xFFFFFFFF	0	0x0000001F	0	0x00000001
#380row-380	4928	0xFFFFFFFF	1	0x0000001F	0	0xFFFFFFFF
#381row-381	4943	0x00000001	0	0x0000001F	1	0x80000000
#382row-382	4958	0x00000001	0	0x0000001F	0	0x00000000
#383row-383	4960	0x00000001	1	0x0000001F	0	0x00000000
#384row-384	4975	0x80000001	0	0x00000020	1	0x80000001
#385row-385	4991	0x80000001	0	0x00000020	0	0x80000001
#386row-386	4995	0x80000001	1	0x00000020	0	0x80000001
#387row-387	5011	0x7FFFFFFF	0	0x00000020	1	0x7FFFFFFF
#388row-388	5027	0x7FFFFFFF	0	0x00000020	0	0x7FFFFFFF
#389row-389	5029	0x7FFFFFFF	1	0x00000020	0	0x7FFFFFFF
#390row-390	5044	0xFFFFFFFF	0	0x00000020	1	0xFFFFFFFF
#391row-391	5060	0xFFFFFFFF	0	0x00000020	0	0xFFFFFFFF
#392row-392	5064	0xFFFFFFFF	1	0x00000020	0	0xFFFFFFFF
#393row-393	5080	0x00000001	0	0x00000020	1	0x00000001
#394row-394	5096	0x00000001	0	0x00000020	0	0x00000001
#395row-395	5098	0x00000001	1	0x00000020	0	0x00000001
#396row-396	5113	0x80000001	0	0x00000021	1	0x00000002
#397row-397	5129	0x80000001	0	0x00000021	0	0x40000000
#398row-398	5144	0x80000001	1	0x00000021	0	0xC0000000
#399row-399	5160	0x7FFFFFFF	0	0x00000021	1	0xFFFFFFFE
#400row-400	5176	0x7FFFFFFF	0	0x00000021	0	0x3FFFFFFF
#401row-401	5178	0x7FFFFFFF	1	0x00000021	0	0x3FFFFFFF
#402row-402	5193	0xFFFFFFFF	0	0x00000021	1	0xFFFFFFFE
#403row-403	5209	0xFFFFFFFF	0	0x00000021	0	0x7FFFFFFF
#404row-404	5224	0xFFFFFFFF	1	0x00000021	0	0xFFFFFFFF
#405row-405	5240	0x00000001	0	0x00000021	1	0x00000002
#406row-406	5255	0x00000001	0	0x00000021	0	0x00000000
#407row-407	5257	0x00000001	1	0x00000021	0	0x00000000
#408row-408	5272	0x80000001	0	0x0000003F	1	0x80000000
#409row-409	5288	0x80000001	0	0x0000003F	0	0x00000001
#410row-410	5303	0x80000001	1	0x0000003F	0	0xFFFFFFFF
#411row-411	5318	0x7FFFFFFF	0	0x0000003F	1	0x80000000
#412row-412	5333	0x7FFFFFFF	0	0x0000003F	0	0x00000000
#413row-413	5335	0x7FFFFFFF	1	0x0000003F	0	0x00000000
#414row-414	5350	0xFFFFFFFF	0	0x0000003F	1	0x80000000
#415row-415	5366	0xFFFFFFFF	0	0x0000003F	0	0x00000001
#416row-416	5381	0xFFFFFFFF	1	0x0000003F	0	0xFFFFFFFF
#417row-417	5396	0x00000001	0	0x0000003F	1	0x80000000
#418row-418	5411	0x00000001	0	0x0000003F	0	0x00000000
#419row-419	5413	0x00000001	1	0x0000003F	0	0x00000000
#420row-420	5428	0x80000001	0	0xFFFFFFFF	1	0x80000000
#421row-421	5444	0x80000001	0	0xFFFFFFFF	0	0x00000001
#422row-422	5459	0x80000001	1	0xFFFFFFFF	0	0xFFFFFFFF
#423row-423	5474	0x7FFFFFFF	0	0xFFFFFFFF	1	0x80000000
#424row-424	5489	0x7FFFFFFF	0	0xFFFFFFFF	0	0x00000000
#425row-425	5491	0x7FFFFFFF	1	0xFFFFFFFF	0	0x00000000
#426row-426	5506	0xFFFFFFFF	0	0xFFFFFFFF	1	0x80000000
#427row-427	5522	0xFFFFFFFF	0	0xFFFFFFFF	0	0x00000001
#428row-428	5537	0xFFFFFFFF	1	0xFFFFFFFF	0	0xFFFFFFFF
#429row-429	5552	0x00000001	0	0xFFFFFFFF	1	0x80000000
#430row-430	5567	0x00000001	0	0xFFFFFFFF	0	0x00000000
#431row-431	5569	0x00000001	1	0xFFFFFFFF	0	0x00000000
#432row-432	5585	0bZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10	0	0x00000000	1	0bXX10XX10XX10XX10XX10XX10XX10XX10
#433row-433	5601	0bZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10	0	0x00000000	0	0bXX10XX10XX10XX10XX10XX10XX10XX10
#434row-434	5605	0bZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10	1	0x00000000	0	0bXX10XX10XX10XX10XX10XX10XX10XX10
#435row-435	5621	0b0ZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX1	0	0x00000005	1	0bXX10XX10XX10XX10XX10XX10XX100000
#436row-436	5637	0b0ZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX1	0	0x00000005	0	0b000000XX10XX10XX10XX10XX10XX10XX
#437row-437	5639	0b0ZX10ZX10ZX10ZX10ZX10ZX10ZX10ZX1	1	0x00000005	0	0b000000XX10XX10XX10XX10XX10XX10XX
#438row-438	5655	0bX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10Z	0	0x0000001F	1	0bX0000000000000000000000000000000
#439row-439	5671	0bX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10Z	0	0x0000001F	0	0b0000000000000000000000000000000X
#440row-440	5686	0bX10ZX10ZX10ZX10ZX10ZX10ZX10ZX10Z	1	0x0000001F	0	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#441row-441	5702	0x00000000	0	0b00000000000000000000000000000X00	1	0x00000000
#442row-442	5705	0x00000000	0	0b00000000000000000000000000000X00	0	0x00000000
#443row-443	5707	0x00000000	1	0b00000000000000000000000000000X00	0	0x00000000
#444row-444	5710	0x00000000	0	0b00000000000000000000000000000Z00	1	0x00000000
#445row-445	5713	0x00000000	0	0b00000000000000000000000000000Z00	0	0x00000000
#446row-446	5715	0x00000000	1	0b00000000000000000000000000000Z00	0	0x00000000

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open Shifter32

Tests

Shifter32Test exercises directions, sign fill, distances, ignored upper amount bits, and selected four-state inputs.

4.3.3.4. ALU32ControlDecoder

IO pins

Pin	Direction	Width	Description
OP	Input	5	Complete opcode
LOCAL_OP	Output	3	OP[2:0]
HIGH_HALF, OUT_OF_RANGE	Output	1 each	OP[3], OP[4]
ARITHMETIC_ENABLE	Output	1	Qualifies carry and overflow
SUB	Output	1	Requests subtraction and enables comparisons
SHIFT_LEFT, SHIFT_ARITHMETIC	Output	1 each	Shifter controls

Behavior

Arithmetic flags are enabled for 0, 1, 8, 9; subtraction for 1, 8, 9. Shift controls are raw Boolean functions, not shift-operation enable flags. They can be high when another result source is selected. OUT_OF_RANGE only detects 16–31; selectors also map reserved 13–15 to zero.

C++ example

namespace alu32_example {
struct Control {
    unsigned LOCAL_OP;
    bool HIGH_HALF, OUT_OF_RANGE, ARITHMETIC_ENABLE, SUB, SHIFT_LEFT, SHIFT_ARITHMETIC;
};
Control control(unsigned op) { // OP is a five-bit input.
    const bool arithmetic = !(op & 16) && !(op & 4) && !(op & 2);
    return {op & 7, bool(op & 8), bool(op & 16), arithmetic,
            arithmetic && bool(op & 9), !(op & 2), bool(op & 1)};
}
}

Unknown inputs and timing

Rewired selector bits preserve X/Z; logic-derived controls follow their gates. Outputs are combinational and need time to settle.

Implementation

Structural implementation

A splitter and selector joiner expose opcode bits; NOT/AND/OR gates derive the enables. No behavioral implementation is registered for this helper.

Examples

All 32 recorded rows of ALU32ControlDecoderTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (438e8bc4f19a50b2). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	OPInput · 5 bit	ARITHMETIC_ENABLEExpected output · 1 bit	HIGH_HALFExpected output · 1 bit	LOCAL_OPExpected output · 3 bit	OUT_OF_RANGEExpected output · 1 bit	SHIFT_ARITHMETICExpected output · 1 bit	SHIFT_LEFTExpected output · 1 bit	SUBExpected output · 1 bit
#0row-0	5	0x00	1	0	0x0	0	0	1	0
#1row-1	9	0x01	1	0	0x1	0	1	1	1
#2row-2	14	0x02	0	0	0x2	0	0	0	0
#3row-3	18	0x03	0	0	0x3	0	1	0	0
#4row-4	24	0x04	0	0	0x4	0	0	1	0
#5row-5	28	0x05	0	0	0x5	0	1	1	0
#6row-6	32	0x06	0	0	0x6	0	0	0	0
#7row-7	36	0x07	0	0	0x7	0	1	0	0
#8row-8	42	0x08	1	1	0x0	0	0	1	1
#9row-9	45	0x09	1	1	0x1	0	1	1	1
#10row-10	50	0x0A	0	1	0x2	0	0	0	0
#11row-11	53	0x0B	0	1	0x3	0	1	0	0
#12row-12	59	0x0C	0	1	0x4	0	0	1	0
#13row-13	62	0x0D	0	1	0x5	0	1	1	0
#14row-14	66	0x0E	0	1	0x6	0	0	0	0
#15row-15	69	0x0F	0	1	0x7	0	1	0	0
#16row-16	73	0x10	0	0	0x0	1	0	1	0
#17row-17	77	0x11	0	0	0x1	1	1	1	0
#18row-18	81	0x12	0	0	0x2	1	0	0	0
#19row-19	85	0x13	0	0	0x3	1	1	0	0
#20row-20	89	0x14	0	0	0x4	1	0	1	0
#21row-21	93	0x15	0	0	0x5	1	1	1	0
#22row-22	97	0x16	0	0	0x6	1	0	0	0
#23row-23	101	0x17	0	0	0x7	1	1	0	0
#24row-24	105	0x18	0	1	0x0	1	0	1	0
#25row-25	108	0x19	0	1	0x1	1	1	1	0
#26row-26	112	0x1A	0	1	0x2	1	0	0	0
#27row-27	115	0x1B	0	1	0x3	1	1	0	0
#28row-28	119	0x1C	0	1	0x4	1	0	1	0
#29row-29	122	0x1D	0	1	0x5	1	1	1	0
#30row-30	126	0x1E	0	1	0x6	1	0	0	0
#31row-31	129	0x1F	0	1	0x7	1	1	0	0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open ALU32ControlDecoder

Tests

ALU32ControlDecoderTest covers every binary opcode and every output control.

4.3.3.5. ALU32CompareUnit

IO pins

Pin	Direction	Width	Description
DIFF	Input	32	A - B from the shared subtractor
CARRY_IN, OVERFLOW_IN	Input	1 each	Subtraction no-borrow and signed overflow
ENABLE	Input	1	Enable comparisons
EQ, LT_SIGNED, LT_UNSIGNED	Output	1 each	Comparison flags
SLT_RESULT, SLTU_RESULT	Output	32 each	Corresponding less-than flag in bit 0; bits 31:1 zero

Behavior

This helper consumes an existing subtraction; it is not an independent two-operand comparator. Signed comparison corrects the difference sign using overflow. All comparisons are zero when disabled. The 32-bit outputs are ALU result words, not 32-bit flags.

C++ example

namespace alu32_example {
struct Compare { bool EQ, LT_SIGNED, LT_UNSIGNED; uint32_t SLT_RESULT, SLTU_RESULT; };
Compare compare(uint32_t diff, bool carry, bool overflow, bool enable) {
    const bool s = enable && (bool(diff >> 31) != overflow);
    const bool u = enable && !carry;
    return {enable && diff == 0, s, u, uint32_t(s), uint32_t(u)};
}
}

Unknown inputs and timing

Disabled AND outputs mask unknown arithmetic inputs. Enabled flags use four-state zero-detection, XOR, and inversion. Upper Boolean-result bits remain constant zero.

Implementation

Structural implementation

ZeroDetect32 forms equality; a sign splitter, XOR, NOT, and AND gates form less-than flags. Joiners extend those flags to words. No behavioral implementation is registered for this helper.

Examples

All 34 recorded rows of ALU32CompareUnitTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (c569123cf5f46ffc). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	CARRY_INInput · 1 bit	DIFFInput · 32 bit	ENABLEInput · 1 bit	OVERFLOW_INInput · 1 bit	EQExpected output · 1 bit	LT_SIGNEDExpected output · 1 bit	LT_UNSIGNEDExpected output · 1 bit	SLTU_RESULTExpected output · 32 bit	SLT_RESULTExpected output · 32 bit
#0row-0	8	0	0x00000000	0	0	0	0	0	0x00000000	0x00000000
#1row-1	17	0	0x00000001	0	0	0	0	0	0x00000000	0x00000000
#2row-2	24	0	0x80000000	0	0	0	0	0	0x00000000	0x00000000
#3row-3	31	0	0xFFFFFFFF	0	0	0	0	0	0x00000000	0x00000000
#4row-4	40	0	0x00000000	1	0	1	0	1	0x00000001	0x00000000
#5row-5	49	0	0x00000001	1	0	0	0	1	0x00000001	0x00000000
#6row-6	56	0	0x80000000	1	0	0	1	1	0x00000001	0x00000001
#7row-7	63	0	0xFFFFFFFF	1	0	0	1	1	0x00000001	0x00000001
#8row-8	72	1	0x00000000	0	0	0	0	0	0x00000000	0x00000000
#9row-9	81	1	0x00000001	0	0	0	0	0	0x00000000	0x00000000
#10row-10	88	1	0x80000000	0	0	0	0	0	0x00000000	0x00000000
#11row-11	95	1	0xFFFFFFFF	0	0	0	0	0	0x00000000	0x00000000
#12row-12	104	1	0x00000000	1	0	1	0	0	0x00000000	0x00000000
#13row-13	113	1	0x00000001	1	0	0	0	0	0x00000000	0x00000000
#14row-14	120	1	0x80000000	1	0	0	1	0	0x00000000	0x00000001
#15row-15	127	1	0xFFFFFFFF	1	0	0	1	0	0x00000000	0x00000001
#16row-16	136	0	0x00000000	0	1	0	0	0	0x00000000	0x00000000
#17row-17	145	0	0x00000001	0	1	0	0	0	0x00000000	0x00000000
#18row-18	152	0	0x80000000	0	1	0	0	0	0x00000000	0x00000000
#19row-19	159	0	0xFFFFFFFF	0	1	0	0	0	0x00000000	0x00000000
#20row-20	168	0	0x00000000	1	1	1	1	1	0x00000001	0x00000001
#21row-21	177	0	0x00000001	1	1	0	1	1	0x00000001	0x00000001
#22row-22	184	0	0x80000000	1	1	0	0	1	0x00000001	0x00000000
#23row-23	191	0	0xFFFFFFFF	1	1	0	0	1	0x00000001	0x00000000
#24row-24	200	1	0x00000000	0	1	0	0	0	0x00000000	0x00000000
#25row-25	209	1	0x00000001	0	1	0	0	0	0x00000000	0x00000000
#26row-26	216	1	0x80000000	0	1	0	0	0	0x00000000	0x00000000
#27row-27	223	1	0xFFFFFFFF	0	1	0	0	0	0x00000000	0x00000000
#28row-28	232	1	0x00000000	1	1	1	1	0	0x00000000	0x00000001
#29row-29	241	1	0x00000001	1	1	0	1	0	0x00000000	0x00000001
#30row-30	248	1	0x80000000	1	1	0	0	0	0x00000000	0x00000000
#31row-31	255	1	0xFFFFFFFF	1	1	0	0	0	0x00000000	0x00000000
#32row-32	264	X	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0	X	0	0	0	0x00000000	0x00000000
#33row-33	267	Z	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0	Z	0	0	0	0x00000000	0x00000000

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open ALU32CompareUnit

Tests

ALU32CompareUnitTest checks enable masking, zero, sign/overflow correction, and Boolean word outputs.

4.3.3.6. ALU32ResultSelector

IO pins

Pin	Direction	Width	Description
ARITHMETIC_RESULT, AND_RESULT, OR_RESULT, XOR_RESULT, SHIFT_RESULT	Input	32 each	Operation-unit results
SLT_RESULT, SLTU_RESULT, A, B	Input	32 each	Comparison results and pass-through operands
LOCAL_OP	Input	3	Index within a group
HIGH_HALF	Input	1	Choose high group
OUT_OF_RANGE	Input	1	Force zero
OUT	Output	32	Selected word

Behavior

Low-group sources are arithmetic, arithmetic, AND, OR, XOR, shift, shift, shift. High-group sources are SLT, SLTU, A, B, zero, zero, zero, zero. OUT_OF_RANGE overrides both groups with zero. Inputs are independently meaningful even when no decoder is attached.

C++ example

namespace alu32_example {
uint32_t select(uint32_t arithmetic, uint32_t and_result, uint32_t or_result,
                uint32_t xor_result, uint32_t shifted, uint32_t slt, uint32_t sltu,
                uint32_t a, uint32_t b, unsigned local, bool high, bool invalid) {
    const std::array<uint32_t,8> low{arithmetic,arithmetic,and_result,or_result,xor_result,shifted,shifted,shifted};
    const std::array<uint32_t,8> upper{slt,sltu,a,b,0,0,0,0};
    return invalid ? 0 : (high ? upper : low).at(local);
}
}

Unknown inputs and timing

Known controls mask unselected paths; unknown controls follow the original mux gate equations. The decoded AND/OR network preserves those equations, including repeated arithmetic/shift choices with unknown selector bits. Outputs settle after gate propagation.

Implementation

Structural implementation

Parallel opcode minterms qualify nine result sources. BIT_0 through BIT_31 are expandable ALU32ResultBit slices: each masks the nine source bits and combines them with a balanced OR tree. Invalid operations select no source and produce zero. Selection has no serial mux chain or stored state. No behavioral implementation is registered for this helper.

RV32ILogicOptimizationTest compares this circuit with the former mux tree across all 1,024 four-state selector combinations, each with four data patterns (4,096 rows).

Examples

All 66 recorded rows of ALU32ResultSelectorTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (056387bf0a8256d0). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	AInput · 32 bit	AND_RESULTInput · 32 bit	ARITHMETIC_RESULTInput · 32 bit	BInput · 32 bit	HIGH_HALFInput · 1 bit	LOCAL_OPInput · 3 bit	OR_RESULTInput · 32 bit	OUT_OF_RANGEInput · 1 bit	SHIFT_RESULTInput · 32 bit	SLTU_RESULTInput · 32 bit	SLT_RESULTInput · 32 bit	XOR_RESULTInput · 32 bit	OUTExpected output · 32 bit
#0row-0	11	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x0	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x12345678
#1row-1	18	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x1	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x12345678
#2row-2	29	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x2	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x03254769
#3row-3	40	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x3	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x3016745A
#4row-4	51	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x4	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x2107654B
#5row-5	63	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x5	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x5670123C
#6row-6	76	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x6	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x5670123C
#7row-7	84	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x7	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x5670123C
#8row-8	95	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x0	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x4761032D
#9row-9	106	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x1	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x7452301E
#10row-10	117	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x2	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x6543210F
#11row-11	128	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x3	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x9ABCDEF0
#12row-12	135	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x4	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#13row-13	140	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x5	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#14row-14	145	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x6	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#15row-15	150	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x7	0x3016745A	0	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#16row-16	156	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x0	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#17row-17	162	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x1	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#18row-18	168	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x2	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#19row-19	174	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x3	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#20row-20	180	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x4	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#21row-21	186	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x5	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#22row-22	192	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x6	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#23row-23	198	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	0	0x7	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#24row-24	204	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x0	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#25row-25	210	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x1	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#26row-26	216	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x2	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#27row-27	222	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x3	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#28row-28	227	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x4	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#29row-29	232	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x5	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#30row-30	237	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x6	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#31row-31	242	0x6543210F	0x03254769	0x12345678	0x9ABCDEF0	1	0x7	0x3016745A	1	0x5670123C	0x7452301E	0x4761032D	0x2107654B	0x00000000
#32row-32	254	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x0	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xEDCBA987
#33row-33	261	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x1	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xEDCBA987
#34row-34	272	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x2	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xFCDAB896
#35row-35	283	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x3	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xCFE98BA5
#36row-36	294	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x4	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xDEF89AB4
#37row-37	306	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x5	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xA98FEDC3
#38row-38	319	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x6	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xA98FEDC3
#39row-39	327	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x7	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xA98FEDC3
#40row-40	338	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x0	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0xB89EFCD2
#41row-41	349	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x1	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x8BADCFE1
#42row-42	360	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x2	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x9ABCDEF0
#43row-43	371	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x3	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x6543210F
#44row-44	378	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x4	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#45row-45	383	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x5	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#46row-46	388	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x6	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#47row-47	393	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x7	0xCFE98BA5	0	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#48row-48	399	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x0	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#49row-49	405	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x1	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#50row-50	411	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x2	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#51row-51	417	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x3	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#52row-52	423	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x4	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#53row-53	429	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x5	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#54row-54	435	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x6	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#55row-55	441	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	0	0x7	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#56row-56	447	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x0	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#57row-57	453	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x1	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#58row-58	459	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x2	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#59row-59	465	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x3	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#60row-60	470	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x4	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#61row-61	475	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x5	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#62row-62	480	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x6	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#63row-63	485	0x9ABCDEF0	0xFCDAB896	0xEDCBA987	0x6543210F	1	0x7	0xCFE98BA5	1	0xA98FEDC3	0x8BADCFE1	0xB89EFCD2	0xDEF89AB4	0x00000000
#64row-64	491	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0	0x0	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	1	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX	0x00000000
#65row-65	494	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0	0x0	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	1	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ	0x00000000

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open ALU32ResultSelector

Tests

ALU32ResultSelectorTest checks all local indices and both group/override controls with distinguishable source words.

4.3.3.7. ALU32FlagUnit

IO pins

Pin	Direction	Width	Description
RESULT	Input	32	Selected final result
ARITHMETIC_ENABLE	Input	1	Enables arithmetic flags
ARITH_CARRY, ARITH_OVERFLOW	Input	1 each	Shared adder flags
ZERO, NEGATIVE, CARRY_OUT, OVERFLOW	Output	1 each	Result and qualified arithmetic flags

Behavior

Zero and negative always describe the final result. Carry and overflow are passed only when enabled. Comparison flags do not belong to this block.

C++ example

namespace alu32_example {
struct Flags { bool ZERO, NEGATIVE, CARRY_OUT, OVERFLOW; };
Flags flags(uint32_t result, bool enable, bool carry, bool overflow) {
    return {result == 0, bool(result >> 31), enable && carry, enable && overflow};
}
}

Unknown inputs and timing

Negative directly exposes result bit 31, including Z; zero uses a gate reduction. Disabled carry/overflow are zero even if their arithmetic inputs are unknown.

Implementation

Structural implementation

ZeroDetect32, a SIGN_BIT rewire, and two AND gates implement the block. The rewire has one 32-bit input (RESULT) and one 1-bit output (SIGN), mapping only RESULT[31] to NEGATIVE; it does not expose 31 unused outputs. This is zero-delay routing, including for X and Z, rather than a logic gate. No behavioral implementation is registered for this helper.

Examples

All 42 recorded rows of ALU32FlagUnitTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59427f8ce65a0ac4). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	ARITHMETIC_ENABLEInput · 1 bit	ARITH_CARRYInput · 1 bit	ARITH_OVERFLOWInput · 1 bit	RESULTInput · 32 bit	CARRY_OUTExpected output · 1 bit	NEGATIVEExpected output · 1 bit	OVERFLOWExpected output · 1 bit	ZEROExpected output · 1 bit
#0row-0	7	0	0	0	0x00000000	0	0	0	1
#1row-1	15	0	0	0	0x00000001	0	0	0	0
#2row-2	22	0	0	0	0x80000000	0	1	0	0
#3row-3	29	0	0	0	0xFFFFFFFF	0	1	0	0
#4row-4	37	1	0	0	0x00000000	0	0	0	1
#5row-5	45	1	0	0	0x00000001	0	0	0	0
#6row-6	52	1	0	0	0x80000000	0	1	0	0
#7row-7	59	1	0	0	0xFFFFFFFF	0	1	0	0
#8row-8	67	0	1	0	0x00000000	0	0	0	1
#9row-9	75	0	1	0	0x00000001	0	0	0	0
#10row-10	82	0	1	0	0x80000000	0	1	0	0
#11row-11	89	0	1	0	0xFFFFFFFF	0	1	0	0
#12row-12	97	1	1	0	0x00000000	1	0	0	1
#13row-13	105	1	1	0	0x00000001	1	0	0	0
#14row-14	112	1	1	0	0x80000000	1	1	0	0
#15row-15	119	1	1	0	0xFFFFFFFF	1	1	0	0
#16row-16	127	0	0	1	0x00000000	0	0	0	1
#17row-17	135	0	0	1	0x00000001	0	0	0	0
#18row-18	142	0	0	1	0x80000000	0	1	0	0
#19row-19	149	0	0	1	0xFFFFFFFF	0	1	0	0
#20row-20	157	1	0	1	0x00000000	0	0	1	1
#21row-21	165	1	0	1	0x00000001	0	0	1	0
#22row-22	172	1	0	1	0x80000000	0	1	1	0
#23row-23	179	1	0	1	0xFFFFFFFF	0	1	1	0
#24row-24	187	0	1	1	0x00000000	0	0	0	1
#25row-25	195	0	1	1	0x00000001	0	0	0	0
#26row-26	202	0	1	1	0x80000000	0	1	0	0
#27row-27	209	0	1	1	0xFFFFFFFF	0	1	0	0
#28row-28	217	1	1	1	0x00000000	1	0	1	1
#29row-29	225	1	1	1	0x00000001	1	0	1	0
#30row-30	232	1	1	1	0x80000000	1	1	1	0
#31row-31	239	1	1	1	0xFFFFFFFF	1	1	1	0
#32row-32	247	0	X	X	0x00000000	0	0	0	1
#33row-33	249	0	Z	Z	0x00000000	0	0	0	1
#34row-34	257	0	0	0	0b0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1	0	0	0	0
#35row-35	264	0	0	0	0b1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1	0	1	0	0
#36row-36	271	0	0	0	0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1	0	X	0	0
#37row-37	274	0	0	0	0bZXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1	0	Z	0	0
#38row-38	277	0	0	0	0b0ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ1	0	0	0	0
#39row-39	284	0	0	0	0b1ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ1	0	1	0	0
#40row-40	291	0	0	0	0bXZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ1	0	X	0	0
#41row-41	294	0	0	0	0bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ1	0	Z	0	0

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open ALU32FlagUnit

Tests

ALU32FlagUnitTest checks result classes, enable masking, carry/overflow combinations, and all four sign-bit values with unrelated lower bits set to X or Z. ALUHierarchyTest verifies the single-bit rewire's interface and exact bit mapping.

4.3.3.8. ALU32

IO pins

Pin	Direction	Width	Description
A, B	Input	32 each	Operands
OP	Input	5	Operation
OUT	Output	32	Result
ZERO, NEGATIVE	Output	1 each	Result zero/sign
CARRY_OUT, OVERFLOW	Output	1 each	Qualified arithmetic flags
EQ, LT_SIGNED, LT_UNSIGNED	Output	1 each	Qualified subtraction comparisons

Behavior

OP	Operation	OUT	Carry/overflow	Comparison flags
0	ADD	A + B	Addition	Zero
1	SUB	A - B	Subtraction	Valid
2	AND	A & B	Zero	Zero
3	OR	A \| B	Zero	Zero
4	XOR	A ^ B	Zero	Zero
5	SLL	A << B[4:0]	Zero	Zero
6	SRL	Logical A >> B[4:0]	Zero	Zero
7	SRA	Arithmetic A >> B[4:0]	Zero	Zero
8	SLT	Signed A < B, extended to 32 bits	Subtraction	Valid
9	SLTU	Unsigned A < B, extended to 32 bits	Subtraction	Valid
10	PASS_A	A	Zero	Zero
11	PASS_B	B	Zero	Zero
12	ZERO	0	Zero	Zero
13–31	Reserved	0	Zero	Zero

For every opcode, ZERO = (OUT == 0) and NEGATIVE = OUT[31]. SLT/SLTU retain subtraction carry/overflow even though their final result is only zero or one. EQ is not an always-on operand-equality indicator. Branch instructions select SUB to obtain all three comparisons. Reserved operations produce ZERO=1, all other flags zero; instruction legality is the decoder's responsibility.

C++ example

namespace alu32_example {
struct Result {
    uint32_t OUT;
    bool ZERO, EQ, LT_SIGNED, LT_UNSIGNED, NEGATIVE, CARRY_OUT, OVERFLOW;
};
Result alu(uint32_t a, uint32_t b, unsigned op) {
    const auto c = control(op);
    const auto ar = addsub(a,b,c.SUB);
    const auto l = logic(a,b);
    const auto sh = shift(a,b,c.SHIFT_LEFT,c.SHIFT_ARITHMETIC);
    const auto cmp = compare(ar.OUT,ar.CARRY_OUT,ar.OVERFLOW,c.SUB);
    const auto out = select(ar.OUT,l.AND_OUT,l.OR_OUT,l.XOR_OUT,sh,
        cmp.SLT_RESULT,cmp.SLTU_RESULT,a,b,c.LOCAL_OP,c.HIGH_HALF,c.OUT_OF_RANGE);
    const auto f = flags(out,c.ARITHMETIC_ENABLE,ar.CARRY_OUT,ar.OVERFLOW);
    return {out,f.ZERO,cmp.EQ,cmp.LT_SIGNED,cmp.LT_UNSIGNED,f.NEGATIVE,f.CARRY_OUT,f.OVERFLOW};
}
}

Unknown inputs and timing

Structural gates can mask unused/unknown inputs. ALU32Behavioral instead makes all outputs unknown if any bit of A, B, or OP is nonbinary, including an unused operand. Its equivalence claim is settled binary behavior, not full four-state or transient equivalence. There is no clock: wait for propagation before sampling.

Implementation

Structural implementation

The root contains CONTROL, ARITHMETIC, LOGIC, SHIFT, COMPARE, RESULT_SELECT, and FLAGS. Arithmetic results feed comparison; control selects a result and qualifies flags. Each group can be expanded independently in the visualizer.

Behavioral implementation

ALU32Behavioral computes the selected operation and flags directly. When its delay twin agrees with that result, the catalog-selected part can use the current operands' gate-list settling time within its per-operation delay-table bound; an older pending result still retains publication order. If the twin cannot answer, the table supplies the timing. The registered contract is rv32i.alu32; structural remains available. Inside a structural ALU the arithmetic, logic, shift, and zero-detect units are always built from gates; each keeps its own behavioral form when used standalone.

Examples

All 46 recorded rows of ALU32Test, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (09507fc65276c4e8). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	AInput · 32 bit	BInput · 32 bit	OPInput · 5 bit	CARRY_OUTExpected output · 1 bit	EQExpected output · 1 bit	LT_SIGNEDExpected output · 1 bit	LT_UNSIGNEDExpected output · 1 bit	NEGATIVEExpected output · 1 bit	OUTExpected output · 32 bit	OVERFLOWExpected output · 1 bit	ZEROExpected output · 1 bit
#0row-0	32	0x00000001	0x00000002	0x00	0	0	0	0	0	0x00000003	0	0
#1row-1	66	0xFFFFFFFF	0x00000001	0x00	1	0	0	0	0	0x00000000	0	1
#2row-2	85	0xFFFFFFFF	0xFFFFFFFF	0x00	1	0	0	0	1	0xFFFFFFFE	0	0
#3row-3	120	0x7FFFFFFF	0x00000001	0x00	0	0	0	0	1	0x80000000	1	0
#4row-4	150	0x80000000	0x80000000	0x00	1	0	0	0	0	0x00000000	1	1
#5row-5	184	0x00000005	0x00000005	0x01	1	1	0	0	0	0x00000000	0	1
#6row-6	209	0x00000000	0x00000001	0x01	0	0	1	1	1	0xFFFFFFFF	0	0
#7row-7	229	0x80000000	0x7FFFFFFF	0x01	1	0	1	0	0	0x00000001	1	0
#8row-8	257	0x7FFFFFFF	0xFFFFFFFF	0x01	0	0	0	1	1	0x80000000	1	0
#9row-9	285	0xF0F0F0F0	0x0FF00FF0	0x02	0	0	0	0	0	0x00F000F0	0	0
#10row-10	301	0xF0F0F0F0	0x0FF00FF0	0x03	0	0	0	0	1	0xFFF0FFF0	0	0
#11row-11	321	0xF0F0F0F0	0x0FF00FF0	0x04	0	0	0	0	1	0xFF00FF00	0	0
#12row-12	350	0x00000001	0x0000001F	0x05	0	0	0	0	1	0x80000000	0	0
#13row-13	378	0x00000001	0x00000020	0x05	0	0	0	0	0	0x00000001	0	0
#14row-14	409	0x80000000	0x0000001F	0x06	0	0	0	0	0	0x00000001	0	0
#15row-15	435	0x80000000	0x00000021	0x06	0	0	0	0	0	0x40000000	0	0
#16row-16	459	0x80000000	0x0000001F	0x07	0	0	0	0	1	0xFFFFFFFF	0	0
#17row-17	485	0x80000000	0x00000021	0x07	0	0	0	0	1	0xC0000000	0	0
#18row-18	520	0xFFFFFFFF	0x00000001	0x08	1	0	1	0	0	0x00000001	0	0
#19row-19	554	0x80000000	0x00000000	0x08	1	0	1	0	0	0x00000001	0	0
#20row-20	588	0x7FFFFFFF	0x80000000	0x08	0	0	0	1	0	0x00000000	1	1
#21row-21	619	0xFFFFFFFF	0x00000001	0x09	1	0	1	0	0	0x00000000	0	1
#22row-22	649	0x00000000	0xFFFFFFFF	0x09	0	0	0	1	0	0x00000001	0	0
#23row-23	671	0x7FFFFFFF	0x80000000	0x09	0	0	0	1	0	0x00000001	1	0
#24row-24	695	0x12345678	0x9ABCDEF0	0x0A	0	0	0	0	0	0x12345678	0	0
#25row-25	711	0x12345678	0x9ABCDEF0	0x0B	0	0	0	0	1	0x9ABCDEF0	0	0
#26row-26	737	0x12345678	0x9ABCDEF0	0x0C	0	0	0	0	0	0x00000000	0	1
#27row-27	743	0x12345678	0x9ABCDEF0	0x0D	0	0	0	0	0	0x00000000	0	1
#28row-28	763	0x12345678	0x9ABCDEF0	0x0E	0	0	0	0	0	0x00000000	0	1
#29row-29	769	0x12345678	0x9ABCDEF0	0x0F	0	0	0	0	0	0x00000000	0	1
#30row-30	789	0x12345678	0x9ABCDEF0	0x10	0	0	0	0	0	0x00000000	0	1
#31row-31	796	0x12345678	0x9ABCDEF0	0x11	0	0	0	0	0	0x00000000	0	1
#32row-32	816	0x12345678	0x9ABCDEF0	0x12	0	0	0	0	0	0x00000000	0	1
#33row-33	823	0x12345678	0x9ABCDEF0	0x13	0	0	0	0	0	0x00000000	0	1
#34row-34	843	0x12345678	0x9ABCDEF0	0x14	0	0	0	0	0	0x00000000	0	1
#35row-35	850	0x12345678	0x9ABCDEF0	0x15	0	0	0	0	0	0x00000000	0	1
#36row-36	870	0x12345678	0x9ABCDEF0	0x16	0	0	0	0	0	0x00000000	0	1
#37row-37	877	0x12345678	0x9ABCDEF0	0x17	0	0	0	0	0	0x00000000	0	1
#38row-38	897	0x12345678	0x9ABCDEF0	0x18	0	0	0	0	0	0x00000000	0	1
#39row-39	904	0x12345678	0x9ABCDEF0	0x19	0	0	0	0	0	0x00000000	0	1
#40row-40	924	0x12345678	0x9ABCDEF0	0x1A	0	0	0	0	0	0x00000000	0	1
#41row-41	931	0x12345678	0x9ABCDEF0	0x1B	0	0	0	0	0	0x00000000	0	1
#42row-42	951	0x12345678	0x9ABCDEF0	0x1C	0	0	0	0	0	0x00000000	0	1
#43row-43	957	0x12345678	0x9ABCDEF0	0x1D	0	0	0	0	0	0x00000000	0	1
#44row-44	977	0x12345678	0x9ABCDEF0	0x1E	0	0	0	0	0	0x00000000	0	1
#45row-45	983	0x12345678	0x9ABCDEF0	0x1F	0	0	0	0	0	0x00000000	0	1

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open ALU32

Tests

ALU32Test checks the integrated binary contract in both fidelities. ALU32RepresentativeSliceTest validates the lower-level construction. RV32IBuildingBlocksDocumentationTest compiles the C++ examples above and checks their outputs against declared binary test actions. Source implementations, including ALU32Behavioral, are in src/modules/composite/.

4.3.3.9. ALU32Core

IO pins

Pin	Direction	Width	Description
A, B	Input	32 each	Operands
OP	Input	5	Operation
OUT	Output	32	Selected result
EQ, LT_SIGNED, LT_UNSIGNED	Output	1 each	Comparisons, valid for subtraction operations

Behavior

ALU32Core retains inputs A[32], B[32], OP[5] and outputs OUT[32], EQ, LT_SIGNED, and LT_UNSIGNED. It omits ZERO, NEGATIVE, CARRY_OUT, and OVERFLOW, so its structural hierarchy has no FLAGS child. The arithmetic unit still computes carry and overflow internally because signed comparison needs them. The general ALU32 retains all flags. Both variants use the same operation codes and settled binary result/compare rules. ALU32CoreTest checks the reduced interface in structural and behavioral fidelities against the same arithmetic vectors as ALU32Test.

C++ example

namespace alu32_example {
struct CoreResult {
    uint32_t OUT;
    bool EQ, LT_SIGNED, LT_UNSIGNED;
};
CoreResult core(uint32_t a, uint32_t b, unsigned op) {
    const auto r = alu(a, b, op);
    return {r.OUT, r.EQ, r.LT_SIGNED, r.LT_UNSIGNED};
}
}

Unknown inputs and timing

The structural form may mask unknown values in unused logic; the behavioral form returns unknown outputs if any bit of A, B, or OP is nonbinary. Their equivalence claim covers settled binary inputs. The unit is combinational and has no clock.

Implementation

Structural implementation

The CONTROL, ARITHMETIC, LOGIC, SHIFT, COMPARE, and RESULT_SELECT groups share the general ALU32 construction. There is no FLAGS group or externally connected flag storage.

Behavioral implementation

The rv32i.alu32-core family uses ALU32Behavioral in its reduced-interface mode. It computes the same result and comparisons as the general behavioral ALU but does not expose the four omitted flags.

Examples

All 46 recorded rows of ALU32CoreTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (0eaa7ada9ecd34f2). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	AInput · 32 bit	BInput · 32 bit	OPInput · 5 bit	EQExpected output · 1 bit	LT_SIGNEDExpected output · 1 bit	LT_UNSIGNEDExpected output · 1 bit	OUTExpected output · 32 bit
#0row-0	26	0x00000001	0x00000002	0x00	0	0	0	0x00000003
#1row-1	55	0xFFFFFFFF	0x00000001	0x00	0	0	0	0x00000000
#2row-2	71	0xFFFFFFFF	0xFFFFFFFF	0x00	0	0	0	0xFFFFFFFE
#3row-3	101	0x7FFFFFFF	0x00000001	0x00	0	0	0	0x80000000
#4row-4	126	0x80000000	0x80000000	0x00	0	0	0	0x00000000
#5row-5	155	0x00000005	0x00000005	0x01	1	0	0	0x00000000
#6row-6	177	0x00000000	0x00000001	0x01	0	1	1	0xFFFFFFFF
#7row-7	197	0x80000000	0x7FFFFFFF	0x01	0	1	0	0x00000001
#8row-8	220	0x7FFFFFFF	0xFFFFFFFF	0x01	0	0	1	0x80000000
#9row-9	248	0xF0F0F0F0	0x0FF00FF0	0x02	0	0	0	0x00F000F0
#10row-10	259	0xF0F0F0F0	0x0FF00FF0	0x03	0	0	0	0xFFF0FFF0
#11row-11	279	0xF0F0F0F0	0x0FF00FF0	0x04	0	0	0	0xFF00FF00
#12row-12	303	0x00000001	0x0000001F	0x05	0	0	0	0x80000000
#13row-13	324	0x00000001	0x00000020	0x05	0	0	0	0x00000001
#14row-14	348	0x80000000	0x0000001F	0x06	0	0	0	0x00000001
#15row-15	367	0x80000000	0x00000021	0x06	0	0	0	0x40000000
#16row-16	389	0x80000000	0x0000001F	0x07	0	0	0	0xFFFFFFFF
#17row-17	408	0x80000000	0x00000021	0x07	0	0	0	0xC0000000
#18row-18	436	0xFFFFFFFF	0x00000001	0x08	0	1	0	0x00000001
#19row-19	463	0x80000000	0x00000000	0x08	0	1	0	0x00000001
#20row-20	490	0x7FFFFFFF	0x80000000	0x08	0	0	1	0x00000000
#21row-21	514	0xFFFFFFFF	0x00000001	0x09	0	1	0	0x00000000
#22row-22	537	0x00000000	0xFFFFFFFF	0x09	0	0	1	0x00000001
#23row-23	559	0x7FFFFFFF	0x80000000	0x09	0	0	1	0x00000001
#24row-24	583	0x12345678	0x9ABCDEF0	0x0A	0	0	0	0x12345678
#25row-25	595	0x12345678	0x9ABCDEF0	0x0B	0	0	0	0x9ABCDEF0
#26row-26	621	0x12345678	0x9ABCDEF0	0x0C	0	0	0	0x00000000
#27row-27	627	0x12345678	0x9ABCDEF0	0x0D	0	0	0	0x00000000
#28row-28	647	0x12345678	0x9ABCDEF0	0x0E	0	0	0	0x00000000
#29row-29	653	0x12345678	0x9ABCDEF0	0x0F	0	0	0	0x00000000
#30row-30	673	0x12345678	0x9ABCDEF0	0x10	0	0	0	0x00000000
#31row-31	680	0x12345678	0x9ABCDEF0	0x11	0	0	0	0x00000000
#32row-32	700	0x12345678	0x9ABCDEF0	0x12	0	0	0	0x00000000
#33row-33	707	0x12345678	0x9ABCDEF0	0x13	0	0	0	0x00000000
#34row-34	727	0x12345678	0x9ABCDEF0	0x14	0	0	0	0x00000000
#35row-35	734	0x12345678	0x9ABCDEF0	0x15	0	0	0	0x00000000
#36row-36	754	0x12345678	0x9ABCDEF0	0x16	0	0	0	0x00000000
#37row-37	761	0x12345678	0x9ABCDEF0	0x17	0	0	0	0x00000000
#38row-38	781	0x12345678	0x9ABCDEF0	0x18	0	0	0	0x00000000
#39row-39	788	0x12345678	0x9ABCDEF0	0x19	0	0	0	0x00000000
#40row-40	808	0x12345678	0x9ABCDEF0	0x1A	0	0	0	0x00000000
#41row-41	815	0x12345678	0x9ABCDEF0	0x1B	0	0	0	0x00000000
#42row-42	835	0x12345678	0x9ABCDEF0	0x1C	0	0	0	0x00000000
#43row-43	841	0x12345678	0x9ABCDEF0	0x1D	0	0	0	0x00000000
#44row-44	861	0x12345678	0x9ABCDEF0	0x1E	0	0	0	0x00000000
#45row-45	867	0x12345678	0x9ABCDEF0	0x1F	0	0	0	0x00000000

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Embedded simulation

Open ALU32Core

Tests

ALU32CoreTest checks structural and behavioral results against the same arithmetic vectors. RV32IBuildingBlocksDocumentationTest replays the binary examples against the C++ reference above.