§ 3.1.2. SRAM¶

This section specifies a single-port asynchronous SRAM, from a one-bit cell to an addressable device. It separates word storage, physical row/column organization, symbolic bitline behavior, and access circuitry. Shared decoding/selection construction and output-enable behavior are described in 3.1.0. Helper Components; the SRAM-specific bitline and access contracts remain distinct.

Component	Description	Structural	Behavioral
`SRAMCell`	Stores one bit using a feedback latch and symbolic write access	Yes	Yes
`SRAMRow`	Groups C cells sharing one wordline	Yes	Yes
`SRAMBitlinePair`	Digital primitive for one shared column's precharge, sensing, and write excitation	Yes	No
`SRAMStorageBank<W>`	Assembles R rows and C shared bitline pairs	Yes	Yes
`SRAMRowDecoder`	Decodes the row portion of a word address	Yes	No
`SRAMPrecharge`	Distributes precharge control to the physical columns	Yes	No
`SRAMWriteDriver`	Generates one bit's complementary write values and masked drive enable	Yes	No
`SRAMSenseAmplifier`	Digital primitive that accepts a valid symbolic read differential	Yes	No
`SRAMColumnSelector<W>`	Routes one word's read pairs and write enables among K column groups	Yes	No
`SRAMAccessControl<W>`	Timed digital primitive sequencing an asynchronous access	Yes	No
`SRAMOutputBuffer<W>`	Compatibility wrapper around the common output-enable primitive	Yes	No
`SRAM<W>`	Complete word-addressed asynchronous SRAM device	Yes	Yes

“Structural” includes explicitly identified terminal digital primitives for bitlines, sensing, output enable, and timing. Those primitives have directly evaluated behavior, but no separate behavioral-fidelity replacement. Only cells, rows, banks, and devices currently have both registered implementations. Structural remains the default for supported small geometries.

Compile the C++ examples in page order. They describe settled binary-control behavior, including state and operation deadlines; empty data optionals represent unknown bits. Construction geometry is assumed valid. Gate propagation and X/Z control-input rules remain in each component's “Unknown inputs and timing” section. These references are not additional simulator components.

Geometry and interface conventions¶

W is the word width: 8, 16, or 32 bits, fixed by the template.
N = depth_words is the number of addressable words, supplied at construction.
K = words_per_row is a power of two from 1 through 64 that divides N. Non-power-of-two depths such as N=6, K=2 are supported.
There are R = N/K physical rows and C = W*K bit columns. Capacity is N*W/8 bytes. A word is not necessarily a whole row.
Word address a selects row a/K and slot a%K. Slot j occupies columns j*W through j*W+W−1 in this model.
SRAM<32> with N=1024, K=4 has 256 rows, 128 columns, 1024 four-byte words, and 4096 bytes. Use behavioral device fidelity for that capacity rather than expanding 32,768 cells.
The device configuration is SRAMDeviceConfig.
The 32-bit word-address port and separate write/read buses are simulator-facing conventions. They are not a pin-for-pin package model with bidirectional DQ. The engine's single-source wires and INPUT/OUTPUT pin types are unchanged.
CE_N, WE_N, and OE_N are active-low; internal enables and byte masks are active-high. X means unknown and Z means high impedance. Storage has no guaranteed initial binary value.

In the visualizer, rows run horizontally and are stacked in row-number order. Cells run left-to-right in column-number order; BITLINE_c sits beneath CELL_c in every row. The complete device places the row decoder to the left, precharge above the bank, and column selection, write drivers, and sensing below. This layout shows the organization of the digital model, not a transistor floorplan.

Conventional 6T SRAM uses wordlines, paired bitlines, precharge, write drivers, and sensing. Here the cell uses a latch-based digital representation, and a bitline pair carries a symbolic differential, not an electrical voltage. The block organization follows those roles without claiming transistor accuracy. See SRAM cells and row/column organization, slides 31–42.

Construction¶

Native Python factories return fully initialized components; the same registered contracts are used by WebAssembly scenarios:

import circuit_backend as simulator

small = simulator.create_sram("SMALL", data_width=16, depth_words=8,
                              words_per_row=2, fidelity="structural")
large = simulator.create_sram("LARGE", data_width=32, depth_words=1024,
                              words_per_row=4, fidelity="behavioral")
cell = simulator.create_sram_component("cell", "CELL")
row = simulator.create_sram_component("row", "ROW", {"columns": "16"})

The device contract is memory.sram.device.W; the bank is memory.sram.bank.W. Cell and row contracts are memory.sram.cell and memory.sram.row. The remaining contract suffixes are bitline-pair, row-decoder, precharge, write-driver, sense-amplifier, column-selector.W, access-control.W, and output-buffer.W. Replace W with 8, 16, or 32. Standalone row/bitline/precharge geometry uses columns/rows/columns respectively.

Factories reject unsupported widths, invalid geometry, unknown parameters, and unsupported requested fidelities. They do not silently expand a large device or substitute behavioral fidelity for an explicit structural request.

Access timing¶

The device is asynchronous: no external clock is required. A selected address/control change starts a finite internal event sequence. Let P be phase_ticks (default 32, permitted 32–10000 simulator ticks).

Time from a new request	Phase	Action
0	Quiet	Disable old wordlines, write drive, sensing, and output; keep old staged buses stable
P	Precharge	Stage the new address/data/mask and precharge all bitline pairs
2P	Release	Release precharge; establish write drive if this is a write
3P	Access	Activate the selected wordline; cells write or develop a read differential
4P	Ready	Enable sensing and, for a read with OE active, the output buffer

Internal paths add propagation delays. Tests compare settled checkpoints, not equal transient waveforms between fidelities. A canceled request cannot be completed by a stale timer. A write canceled before row activation does not change storage; canceling after activation can leave a completed write and does not roll it back. Hold inputs stable for a complete access. These delays are deliberately conservative simulator units, not calibrated nanoseconds or a vendor setup/hold specification. No automatic cache-latency claim follows from them.

All component examples follow the same IO/behavior/implementation/test pattern as §3.1.1. The C++ references describe each component's binary-control contract, rather than only one selected operation. Example tables are generated from every recorded test checkpoint, include checkpoint number and absolute time, and scroll within the page.

3.1.2.1. `SRAMCell`¶

Stores one bit using a feedback latch and symbolic write access.

IO pins¶

Pin	Direction	Width	Description
`WL`	Input	1	Selects the cell's row
`DRIVE`	Input	1	Strong write excitation; not asserted for reads or precharge
`BL, BL_BAR`	Input	1 each	Symbolic complementary write values
`Q, Q_BAR`	Output	1 each	Stored bit and its complement

Behavior¶

With WL = DRIVE = 1, a complementary binary pair writes Q = BL. If either enable is 0, the cell holds its previous state. Merely selecting the row does not write. The DRIVE signal is an explicit digital distinction between write excitation and read sensing; it is not an extra physical pin on a 6T cell.

C++ example¶

#include <optional>
struct SRAMCellReference {
    std::optional<bool> q; // Empty means unknown, including power-up.
    std::optional<bool> q_bar() const {
        return q ? std::optional(!*q) : std::nullopt;
    }
    void update(bool wl, bool drive, std::optional<bool> bl,
                std::optional<bool> bar) {
        if (wl && drive)
            q = bl && bar && *bl != *bar ? bl : std::nullopt;
    }
};

Unknown inputs and timing¶

Starts unknown. An enabled noncomplementary or X/Z write pair makes storage unknown; a later valid write restores a known bit. Unknown enables can poison state when a write is possible. The structural access primitive has one tick of delay, followed by NAND-latch propagation.

Implementation¶

Structural implementation¶

ACCESS converts symbolic write excitation into active-low set/reset controls. STATE is the existing SRLatch, containing two feedback NAND gates. This is a digital latch-based representation, not a six-transistor electrical circuit.

Behavioral implementation¶

A stored four-state value implements the same settled cell contract without the latch topology. SRAMContractTest compares both implementations.

The behavioral cell's visualizer displays recorded Q and Q_BAR values, with WL and DRIVE indicators. These follow timeline scrubbing; the structural view continues to show its access circuit and latch.

Examples¶

All 9 recorded rows of SRAMCellTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`BL`Input · 1 bit	`BL_BAR`Input · 1 bit	`DRIVE`Input · 1 bit	`WL`Input · 1 bit	`Q`Expected output · 1 bit	`Q_BAR`Expected output · 1 bit
#0`unknown-startup`	2	`1`	`1`	`0`	`0`	`X`	`X`
#1`write-zero`	7	`0`	`1`	`1`	`1`	`0`	`1`
#2`hold`	10	`0`	`1`	`0`	`0`	`0`	not checked
#3`read-is-not-write`	12	`1`	`1`	`0`	`1`	`0`	not checked
#4`write-one`	17	`1`	`0`	`1`	`1`	`1`	`0`
#5`deselect-before-drive-change`	20	`1`	`0`	`0`	`0`	`1`	not checked
#6`unselected-write-drive`	22	`0`	`1`	`1`	`0`	`1`	not checked
#7`unknown-write`	27	`X`	`X`	`1`	`1`	`X`	not checked
#8`recover-zero`	32	`0`	`1`	`1`	`1`	`0`	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The sequence establishes zero, holds it, selects the cell for a read without writing, writes one, rejects an unselected write, captures unknown data, and recovers with a valid write.

Embedded simulation¶

The standalone SRAMCellTest opens this component as SRAM_ROOT. Use the explorer to compare structural and behavioral fidelity.

Open SRAMCell in the simulator

Source and tests¶

Test	Coverage
`SRAMCellTest`	The complete standalone sequence shown above
`SRAMContractTest`	Structural/behavioral equivalence; device and bank widths 8/16/32, multiple geometries and byte masks, mixed bank selection, and invalid configuration rejection

3.1.2.2. `SRAMRow`¶

Groups C cells sharing one wordline.

IO pins¶

Pin	Direction	Width	Description
`WL`	Input	1	Shared wordline
`DRIVE_c`	Input	1 each	Write excitation for column c
`BL_c, BL_BAR_c`	Input	1 each	Column write values
`Q_c`	Output	1 each	Each cell's stored value; feeds the column bitline model

Behavior¶

The construction parameter columns = C creates exactly C cells. Each cell receives the shared wordline and its own column excitation. There is no address decoder, clock, reset, or word read port inside a row. The row may contain several addressable words.

C++ example¶

#include <cstddef>
#include <vector>
struct SRAMRowReference {
    std::vector<SRAMCellReference> cells;
    explicit SRAMRowReference(std::size_t columns) : cells(columns) {}
    void update(bool wl, const std::vector<bool>& drive,
                const std::vector<std::optional<bool>>& bl,
                const std::vector<std::optional<bool>>& bar) {
        for (std::size_t c = 0; c < cells.size(); ++c)
            cells[c].update(wl, drive.at(c), bl.at(c), bar.at(c));
    }
    std::optional<bool> q(std::size_t c) const { return cells.at(c).q; }
};

Unknown inputs and timing¶

Startup and enabled unknown writes follow SRAMCell. columns accepts 1–4096; this is a simulator expansion limit, not a physical row-size claim. Inputs must settle before expecting the row's outputs to settle.

Implementation¶

Structural implementation¶

Contains CELL_0 through CELL_(C−1). Cells are registered families, so a structural row can contain behavioral cells.

Behavioral implementation¶

Stores C four-state values and applies the per-column write controls directly. It keeps the same expanded pin interface.

Examples¶

All 5 recorded rows of SRAMRowTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`BL_0`Input · 1 bit	`BL_1`Input · 1 bit	`BL_BAR_0`Input · 1 bit	`BL_BAR_1`Input · 1 bit	`DRIVE_0`Input · 1 bit	`DRIVE_1`Input · 1 bit	`WL`Input · 1 bit	`Q_0`Expected output · 1 bit	`Q_1`Expected output · 1 bit
#0`unknown-startup`	2	`1`	`0`	`0`	`1`	`0`	`0`	`0`	`X`	`X`
#1`write-two-columns`	7	`1`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`0`
#2`release`	10	`1`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	`0`
#3`prepare-masked-write`	12	`0`	`1`	`1`	`0`	`0`	`1`	`0`	`1`	`0`
#4`write-only-column-one`	17	`0`	`1`	`1`	`0`	`0`	`1`	`1`	`1`	`1`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The two-column example writes different bits, deselects the row, then changes only column 1 while column 0's drive is disabled.

Embedded simulation¶

The standalone SRAMRowTest opens this component as SRAM_ROOT. Use the explorer to compare structural and behavioral fidelity.

Open SRAMRow in the simulator

Source and tests¶

Test	Coverage
`SRAMRowTest`	The complete standalone sequence shown above
`SRAMContractTest`	Structural/behavioral equivalence; device and bank widths 8/16/32, multiple geometries and byte masks, mixed bank selection, and invalid configuration rejection

3.1.2.3. `SRAMBitlinePair`¶

Digital primitive for one shared column's precharge, sensing, and write excitation.

IO pins¶

Pin	Direction	Width	Description
`PRECHARGE`	Input	1	Charge/equalize the pair while all rows and write drivers are inactive
`DRIVE`	Input	1	Enable strong write drive
`WRITE_BL, WRITE_BL_BAR`	Input	1 each	Write driver's complementary values
`WL_r, Q_r`	Input	1 each	Wordline and stored bit contribution from row r
`BL, BL_BAR`	Output	1 each	Symbolic bitline state, not measured voltage
`VALID`	Output	1	Known read differential is available
`CELL_DRIVE`	Output	1	Write excitation sent to the column's cells
`CELL_BL, CELL_BL_BAR`	Output	1 each	Write values delivered to cells

Behavior¶

The construction parameter rows = R supplies one contribution per row. Precharge sets the symbolic pair to (1,1) and prepares it for reading. Releasing precharge retains that state. Selecting one row develops (Q, !Q); VALID is high only for a known bit. Releasing a used row requires another precharge before the next read. During writes, the driver determines the pair and CELL_DRIVE is high. Cells still decide whether their wordline permits writing.

Multiple selected rows, an unknown wordline/drive/precharge, or precharge overlapping a selected row/write drive invalidate the pair and suppress cell drive. These are conservative digital rules, not a calculation of electrical contention.

C++ example¶

#include <optional>
#include <vector>
struct SRAMBitlineReference {
    std::optional<bool> bl, bar, cell_bl, cell_bar;
    bool valid = false, cell_drive = false;
    bool prepared = false;
    std::optional<std::size_t> reading_row;
    void update(bool precharge, bool drive, std::optional<bool> write_bl,
                std::optional<bool> write_bar, const std::vector<bool>& wl,
                const std::vector<std::optional<bool>>& cells) {
        valid = cell_drive = false; cell_bl.reset(); cell_bar.reset();
        std::size_t count = 0, row = 0;
        for (std::size_t r = 0; r < wl.size(); ++r)
            if (wl[r]) { ++count; row = r; }
        auto invalidate = [&] {
            bl.reset(); bar.reset(); prepared = false; reading_row.reset();
        };
        if (count > 1 || (precharge && (drive || count))) { invalidate(); return; }
        if (precharge) {
            bl = bar = true; prepared = true; reading_row.reset();
        } else if (drive) {
            bl = cell_bl = write_bl; bar = cell_bar = write_bar;
            cell_drive = true; prepared = false; reading_row.reset();
        } else if (count) {
            if (!prepared || (reading_row && *reading_row != row)) {
                invalidate(); return;
            }
            reading_row = row; bl = cells.at(row);
            bar = bl ? std::optional(!*bl) : std::nullopt;
            valid = bl.has_value();
        } else if (reading_row) {
            prepared = false; reading_row.reset(); // Pair retains its last value.
        }
    }
};

Unknown inputs and timing¶

The pair starts (X,X). The example covers all binary control combinations, including conflicts, and uses empty optionals for unknown data. X/Z control inputs additionally invalidate the pair. Outputs have a one-tick delay, omitted from the settled reference.

Implementation¶

Structural implementation¶

A registered terminal digital primitive. It is the explicit abstraction boundary for shared bitline behavior, with state recording through ordinary output wires. There is no multi-driver net resolver, capacitance, voltage, transistor strength, or leakage model. No separate compact implementation is registered because this primitive already performs direct evaluation.

Examples¶

All 13 recorded rows of SRAMBitlinePairTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`DRIVE`Input · 1 bit	`PRECHARGE`Input · 1 bit	`Q_0`Input · 1 bit	`Q_1`Input · 1 bit	`WL_0`Input · 1 bit	`WL_1`Input · 1 bit	`WRITE_BL`Input · 1 bit	`WRITE_BL_BAR`Input · 1 bit	`BL`Expected output · 1 bit	`BL_BAR`Expected output · 1 bit	`CELL_BL`Expected output · 1 bit	`CELL_BL_BAR`Expected output · 1 bit	`CELL_DRIVE`Expected output · 1 bit	`VALID`Expected output · 1 bit
#0`unknown-startup`	1	`0`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	`X`	`X`	not checked	not checked	not checked	`0`
#1`precharge`	3	`0`	`1`	`0`	`1`	`0`	`0`	`0`	`1`	`1`	`1`	not checked	not checked	`0`	not checked
#2`retain-charge`	5	`0`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	`1`	`1`	not checked	not checked	not checked	not checked
#3`read-row-zero`	7	`0`	`0`	`0`	`1`	`1`	`0`	`0`	`1`	`0`	`1`	not checked	not checked	`0`	`1`
#4`release-row`	9	`0`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	`0`
#5`missing-precharge`	11	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`X`	not checked	not checked	not checked	not checked	`0`
#6`deselect`	13	`0`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	`0`
#7`precharge-again`	15	`0`	`1`	`0`	`1`	`0`	`0`	`0`	`1`	`1`	`1`	not checked	not checked	not checked	not checked
#8`release-precharge`	17	`0`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	`1`	not checked	not checked	not checked	not checked	not checked
#9`read-row-one`	19	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`0`	not checked	not checked	not checked	`1`
#10`two-row-conflict`	21	`0`	`0`	`0`	`1`	`1`	`1`	`0`	`1`	`X`	not checked	not checked	not checked	`0`	`0`
#11`write-drive`	23	`1`	`0`	`0`	`1`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	not checked	`1`	not checked
#12`precharge-write-conflict`	25	`1`	`1`	`0`	`1`	`0`	`0`	`0`	`1`	`X`	not checked	not checked	not checked	`0`	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The sequence includes precharge, retained charge, reads from both rows, a missing-precharge failure, two-row contention, write drive, and a precharge/write conflict.

Embedded simulation¶

The standalone SRAMBitlinePairTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMBitlinePair in the simulator

Source and tests¶

Test	Coverage
`SRAMBitlinePairTest`	The complete standalone sequence shown above

3.1.2.4. `SRAMStorageBank<W>`¶

Assembles R rows and C shared bitline pairs.

IO pins¶

Pin	Direction	Width	Description
`WL_r`	Input	1 each	Row selections supplied by the decoder
`PRECHARGE_c`	Input	1 each	Precharge enable per bit column
`DRIVE_c`	Input	1 each	Column write drive
`WRITE_BL_c, WRITE_BL_BAR_c`	Input	1 each	Column write values
`BL_c, BL_BAR_c, VALID_c`	Output	1 each	Symbolic pair and read-valid result per column

Behavior¶

For W-bit words, N words, and K words per row, the bank has R = N/K rows and C = W*K columns. It contains exactly N*W cells. There is no complete word-address interface: row decoding, column selection, sensing, and access sequencing remain outside the bank. It does not expose every stored word as WORD_n, unlike FFStorageBank.

C++ example¶

#include <cstddef>
#include <vector>
struct SRAMBankReference {
    std::vector<SRAMRowReference> rows;
    std::vector<SRAMBitlineReference> columns;
    SRAMBankReference(std::size_t r, std::size_t c)
        : rows(r, SRAMRowReference(c)), columns(c) {}
    void update(const std::vector<bool>& wl, const std::vector<bool>& precharge,
                const std::vector<bool>& drive,
                const std::vector<std::optional<bool>>& bl,
                const std::vector<std::optional<bool>>& bar) {
        for (std::size_t c = 0; c < columns.size(); ++c) {
            std::vector<std::optional<bool>> q;
            for (const auto& row : rows) q.push_back(row.q(c));
            auto& pair = columns[c];
            pair.update(precharge.at(c), drive.at(c), bl.at(c), bar.at(c), wl, q);
            for (std::size_t r = 0; r < rows.size(); ++r)
                rows[r].cells[c].update(wl.at(r), pair.cell_drive, pair.cell_bl, pair.cell_bar);
        }
    }
    // BL_c / BL_BAR_c / VALID_c are columns[c].bl / bar / valid.
};

Unknown inputs and timing¶

The example composes the cell and bitline references, including unknown startup, precharge, reads, writes, and binary control conflicts. It assumes controls are settled and binary; X/Z controls follow the rules above. Both bank implementations are limited to 4096 cells because their interface exposes every row and column. A large compact device uses the word-address port instead.

Implementation¶

Structural implementation¶

ROW_r owns C SRAMCell instances. BITLINE_c receives that column's cell values from every row and distributes write excitation back to those cells. Rows own cells; bitline components do not duplicate storage.

Behavioral implementation¶

A flat four-state cell array plus per-column bitline state replaces the rows and cells. The same digital bitline primitive rules are reused. This proves equivalence to the documented abstraction, not independently to analog SRAM physics. Bank replacement leaves the surrounding decoder, precharge, drivers, selector, and sense amplifiers visible.

Examples¶

All 16 recorded rows of SRAMStorageBankTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`DRIVE_0`Input · 1 bit	`DRIVE_1`Input · 1 bit	`DRIVE_10`Input · 1 bit	`DRIVE_11`Input · 1 bit	`DRIVE_12`Input · 1 bit	`DRIVE_13`Input · 1 bit	`DRIVE_14`Input · 1 bit	`DRIVE_15`Input · 1 bit	`DRIVE_2`Input · 1 bit	`DRIVE_3`Input · 1 bit	`DRIVE_4`Input · 1 bit	`DRIVE_5`Input · 1 bit	`DRIVE_6`Input · 1 bit	`DRIVE_7`Input · 1 bit	`DRIVE_8`Input · 1 bit	`DRIVE_9`Input · 1 bit	`PRECHARGE_0`Input · 1 bit	`PRECHARGE_1`Input · 1 bit	`PRECHARGE_10`Input · 1 bit	`PRECHARGE_11`Input · 1 bit	`PRECHARGE_12`Input · 1 bit	`PRECHARGE_13`Input · 1 bit	`PRECHARGE_14`Input · 1 bit	`PRECHARGE_15`Input · 1 bit	`PRECHARGE_2`Input · 1 bit	`PRECHARGE_3`Input · 1 bit	`PRECHARGE_4`Input · 1 bit	`PRECHARGE_5`Input · 1 bit	`PRECHARGE_6`Input · 1 bit	`PRECHARGE_7`Input · 1 bit	`PRECHARGE_8`Input · 1 bit	`PRECHARGE_9`Input · 1 bit	`WL_0`Input · 1 bit	`WL_1`Input · 1 bit	`WRITE_BL_0`Input · 1 bit	`WRITE_BL_1`Input · 1 bit	`WRITE_BL_10`Input · 1 bit	`WRITE_BL_11`Input · 1 bit	`WRITE_BL_12`Input · 1 bit	`WRITE_BL_13`Input · 1 bit	`WRITE_BL_14`Input · 1 bit	`WRITE_BL_15`Input · 1 bit	`WRITE_BL_2`Input · 1 bit	`WRITE_BL_3`Input · 1 bit	`WRITE_BL_4`Input · 1 bit	`WRITE_BL_5`Input · 1 bit	`WRITE_BL_6`Input · 1 bit	`WRITE_BL_7`Input · 1 bit	`WRITE_BL_8`Input · 1 bit	`WRITE_BL_9`Input · 1 bit	`WRITE_BL_BAR_0`Input · 1 bit	`WRITE_BL_BAR_1`Input · 1 bit	`WRITE_BL_BAR_10`Input · 1 bit	`WRITE_BL_BAR_11`Input · 1 bit	`WRITE_BL_BAR_12`Input · 1 bit	`WRITE_BL_BAR_13`Input · 1 bit	`WRITE_BL_BAR_14`Input · 1 bit	`WRITE_BL_BAR_15`Input · 1 bit	`WRITE_BL_BAR_2`Input · 1 bit	`WRITE_BL_BAR_3`Input · 1 bit	`WRITE_BL_BAR_4`Input · 1 bit	`WRITE_BL_BAR_5`Input · 1 bit	`WRITE_BL_BAR_6`Input · 1 bit	`WRITE_BL_BAR_7`Input · 1 bit	`WRITE_BL_BAR_8`Input · 1 bit	`WRITE_BL_BAR_9`Input · 1 bit	`BL_0`Expected output · 1 bit	`BL_1`Expected output · 1 bit	`BL_10`Expected output · 1 bit	`BL_11`Expected output · 1 bit	`BL_12`Expected output · 1 bit	`BL_13`Expected output · 1 bit	`BL_14`Expected output · 1 bit	`BL_15`Expected output · 1 bit	`BL_2`Expected output · 1 bit	`BL_3`Expected output · 1 bit	`BL_4`Expected output · 1 bit	`BL_5`Expected output · 1 bit	`BL_6`Expected output · 1 bit	`BL_7`Expected output · 1 bit	`BL_8`Expected output · 1 bit	`BL_9`Expected output · 1 bit	`BL_BAR_0`Expected output · 1 bit	`BL_BAR_1`Expected output · 1 bit	`BL_BAR_10`Expected output · 1 bit	`BL_BAR_11`Expected output · 1 bit	`BL_BAR_12`Expected output · 1 bit	`BL_BAR_13`Expected output · 1 bit	`BL_BAR_14`Expected output · 1 bit	`BL_BAR_15`Expected output · 1 bit	`BL_BAR_2`Expected output · 1 bit	`BL_BAR_3`Expected output · 1 bit	`BL_BAR_4`Expected output · 1 bit	`BL_BAR_5`Expected output · 1 bit	`BL_BAR_6`Expected output · 1 bit	`BL_BAR_7`Expected output · 1 bit	`BL_BAR_8`Expected output · 1 bit	`BL_BAR_9`Expected output · 1 bit	`VALID_0`Expected output · 1 bit	`VALID_1`Expected output · 1 bit	`VALID_10`Expected output · 1 bit	`VALID_11`Expected output · 1 bit	`VALID_12`Expected output · 1 bit	`VALID_13`Expected output · 1 bit	`VALID_14`Expected output · 1 bit	`VALID_15`Expected output · 1 bit	`VALID_2`Expected output · 1 bit	`VALID_3`Expected output · 1 bit	`VALID_4`Expected output · 1 bit	`VALID_5`Expected output · 1 bit	`VALID_6`Expected output · 1 bit	`VALID_7`Expected output · 1 bit	`VALID_8`Expected output · 1 bit	`VALID_9`Expected output · 1 bit
#0`idle`	2	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#1`prepare-write-row-0`	5	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#2`write-row-0`	10	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#3`release-row-0`	13	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#4`prepare-write-row-1`	16	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#5`write-row-1`	21	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#6`release-row-1`	24	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#7`release-drivers`	27	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#8`precharge-row-0`	29	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#9`release-precharge-0`	31	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#10`read-row-0`	33	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`
#11`end-read-0`	35	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#12`precharge-row-1`	37	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#13`release-precharge-1`	39	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked
#14`read-row-1`	41	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`
#15`end-read-1`	43	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	`0`	`1`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	`0`	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked	not checked

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The 4×8 bank is arranged as two rows of 16 cells. Every cell is written in a row-dependent alternating pattern, then both rows are read through explicit precharge/release/select sequences.

Embedded simulation¶

The standalone SRAMStorageBankTest opens this component as SRAM_ROOT. Use the explorer to compare structural and behavioral fidelity.

Open SRAMStorageBank<W> in the simulator

Source and tests¶

Test	Coverage
`SRAMStorageBankTest`	The complete standalone sequence shown above
`SRAMContractTest`	Structural/behavioral equivalence; device and bank widths 8/16/32, multiple geometries and byte masks, mixed bank selection, and invalid configuration rejection

3.1.2.5. `SRAMRowDecoder`¶

Decodes the row portion of a word address.

IO pins¶

Pin	Direction	Width	Description
`WORD_ADDR`	Input	32	Complete word index
`ENABLE`	Input	1	Permit row activation
`WL_r`	Output	1 each	One-hot row selection

Behavior¶

For K words per row, the row number is WORD_ADDR / K. The low log2(K) bits select a word within the row and are ignored here. A known address outside N words selects no row. This decoder is not a DRAM ACTIVATE command or an externally retained open-row protocol.

C++ example¶

#include <cstddef>
#include <cstdint>
#include <vector>
std::vector<bool> sram_rows_ref(std::uint32_t address, bool enable,
                                std::size_t words, std::size_t words_per_row) {
    std::vector<bool> result(words / words_per_row, false);
    if (enable && address < words) result[address / words_per_row] = true;
    return result;
}

Unknown inputs and timing¶

Unknown address bits propagate through the gates and may produce unknown wordlines; the bitline model then suppresses writes. A known low ENABLE deselects all rows even with an unknown address. The structural decoder accepts up to 512 words; complete structural devices apply the stricter W-dependent cell limit.

Implementation¶

Structural implementation¶

An address splitter, complemented address bits, and balanced AND trees implement the row matches. The shared decodeMatch construction routine builds those trees after this wrapper extracts the row-address bits. No storage or direct host indexing is used; gate names and hierarchy remain unchanged. See helper reuse boundaries.

Examples¶

All 9 recorded rows of SRAMRowDecoderTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`ENABLE`Input · 1 bit	`WORD_ADDR`Input · 32 bit	`WL_0`Expected output · 1 bit	`WL_1`Expected output · 1 bit	`WL_2`Expected output · 1 bit
#0`disabled`	8	`0`	`0x00000000`	`0`	`0`	`0`
#1`address-0`	12	`1`	`0x00000000`	`1`	`0`	`0`
#2`address-1`	14	`1`	`0x00000001`	`1`	`0`	`0`
#3`address-2`	19	`1`	`0x00000002`	`0`	`1`	`0`
#4`address-3`	21	`1`	`0x00000003`	`0`	`1`	`0`
#5`address-4`	26	`1`	`0x00000004`	`0`	`0`	`1`
#6`address-5`	28	`1`	`0x00000005`	`0`	`0`	`1`
#7`address-6`	33	`1`	`0x00000006`	`0`	`0`	`0`
#8`address-4294967295`	42	`1`	`0xFFFFFFFF`	`0`	`0`	`0`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Six words arranged two per row demonstrate both word slots in each of three rows, an out-of-range address, and an address with high bits set.

Embedded simulation¶

The standalone SRAMRowDecoderTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMRowDecoder in the simulator

Source and tests¶

Test	Coverage
`SRAMRowDecoderTest`	The complete standalone sequence shown above

3.1.2.6. `SRAMPrecharge`¶

Distributes precharge control to the physical columns.

IO pins¶

Pin	Direction	Width	Description
`ENABLE`	Input	1	Request precharge
`PRECHARGE_c`	Output	1 each	Buffered request for column c

Behavior¶

The construction parameter columns = C creates C buffered precharge controls. This block distributes control; the corresponding SRAMBitlinePair owns the symbolic charged state. Precharge must occur with wordlines and write drivers inactive.

C++ example¶

#include <cstddef>
#include <vector>
std::vector<bool> sram_precharge_ref(bool enable, std::size_t columns) {
    return std::vector<bool>(columns, enable);
}

Unknown inputs and timing¶

Each buffer propagates X/Z as unknown logic. Outputs settle one gate tick after the input. Precharge completion in the complete device includes the downstream bitline delay.

Implementation¶

Structural implementation¶

One AND buffer with a constant-high input per column. These outputs actually drive the bitline primitives; the block is not a visual-only grouping.

Examples¶

All 4 recorded rows of SRAMPrechargeTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`ENABLE`Input · 1 bit	`PRECHARGE_0`Expected output · 1 bit	`PRECHARGE_1`Expected output · 1 bit
#0`disabled`	1	`0`	`0`	`0`
#1`enabled`	3	`1`	`1`	`1`
#2`released`	5	`0`	`0`	`0`
#3`unknown-enable`	7	`X`	`X`	`X`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The two-column example asserts and releases precharge and shows an unknown control propagating to both outputs.

Embedded simulation¶

The standalone SRAMPrechargeTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMPrecharge in the simulator

Source and tests¶

Test	Coverage
`SRAMPrechargeTest`	The complete standalone sequence shown above

3.1.2.7. `SRAMWriteDriver`¶

Generates one bit's complementary write values and masked drive enable.

IO pins¶

Pin	Direction	Width	Description
`D`	Input	1	Data bit
`ENABLE`	Input	1	Write phase active
`MASK`	Input	1	Enable this bit's byte lane
`BL, BL_BAR`	Output	1 each	Data and complementary data
`DRIVE`	Output	1	ENABLE AND MASK

Behavior¶

BL = D, BL_BAR = !D, and DRIVE = ENABLE && MASK. The values may remain present while DRIVE = 0; that does not write storage. There is one driver per external data bit. All eight drivers in a byte receive the same byte-mask input.

C++ example¶

struct SRAMDriveReference { bool bl, bar, drive; };
SRAMDriveReference sram_drive_ref(bool data, bool enable, bool mask) {
    return {data, !data, enable && mask};
}

Unknown inputs and timing¶

Unknown data produces an unknown pair. Unknown drive control is rejected by the bitline primitive and does not authorize a write. Complement generation includes its own gate delay; the access sequencer establishes write drive before activating the row.

Implementation¶

Structural implementation¶

ENABLED_BYTE is an AND gate, DATA is a buffer, and COMPLEMENT is a NOT gate. No electrical drive strength is calculated.

Examples¶

All 8 recorded rows of SRAMWriteDriverTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`D`Input · 1 bit	`ENABLE`Input · 1 bit	`MASK`Input · 1 bit	`BL`Expected output · 1 bit	`BL_BAR`Expected output · 1 bit	`DRIVE`Expected output · 1 bit
#0`data-0-enable-0-mask-0`	2	`0`	`0`	`0`	`0`	`1`	`0`
#1`data-0-enable-0-mask-1`	4	`0`	`0`	`1`	`0`	`1`	`0`
#2`data-0-enable-1-mask-0`	6	`0`	`1`	`0`	`0`	`1`	`0`
#3`data-0-enable-1-mask-1`	8	`0`	`1`	`1`	`0`	`1`	`1`
#4`data-1-enable-0-mask-0`	11	`1`	`0`	`0`	`1`	`0`	`0`
#5`data-1-enable-0-mask-1`	13	`1`	`0`	`1`	`1`	`0`	`0`
#6`data-1-enable-1-mask-0`	15	`1`	`1`	`0`	`1`	`0`	`0`
#7`data-1-enable-1-mask-1`	17	`1`	`1`	`1`	`1`	`0`	`1`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

All eight binary combinations of data, enable, and byte mask are included.

Embedded simulation¶

The standalone SRAMWriteDriverTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMWriteDriver in the simulator

Source and tests¶

Test	Coverage
`SRAMWriteDriverTest`	The complete standalone sequence shown above

3.1.2.8. `SRAMSenseAmplifier`¶

Digital primitive that accepts a valid symbolic read differential.

IO pins¶

Pin	Direction	Width	Description
`BL, BL_BAR`	Input	1 each	Selected symbolic bitline pair
`VALID`	Input	1	The bitline model has a known read differential
`ENABLE`	Input	1	Sensing phase active
`Q`	Output	1	Resolved read bit, or X

Behavior¶

A known complementary pair produces Q = BL only when VALID = ENABLE = 1. Equal pairs, disabled sensing, and invalid input produce X. In particular, (1,1) from precharge must not be mistaken for a stored one.

C++ example¶

#include <optional>
std::optional<bool> sram_sense_ref(bool bl, bool bar, bool valid, bool enable) {
    if (enable && valid && bl != bar) return bl;
    return std::nullopt;
}

Unknown inputs and timing¶

X/Z or a noncomplementary pair cannot produce a known bit. Output delay is one tick. This model does not calculate differential voltage, gain, noise, or sense-amplifier offset.

Implementation¶

Structural implementation¶

A registered terminal digital primitive. It provides the sensing boundary used by the structural device; there is no separate behavioral replacement.

Examples¶

All 5 recorded rows of SRAMSenseAmplifierTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`BL`Input · 1 bit	`BL_BAR`Input · 1 bit	`ENABLE`Input · 1 bit	`VALID`Input · 1 bit	`Q`Expected output · 1 bit
#0`disabled`	1	`1`	`1`	`0`	`0`	`X`
#1`equal-pair-is-not-data`	3	`1`	`1`	`1`	`0`	`X`
#2`sense-zero`	5	`0`	`1`	`1`	`1`	`0`
#3`sense-one`	7	`1`	`0`	`1`	`1`	`1`
#4`invalid-pair`	9	`1`	`1`	`1`	`1`	`X`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Disabled sensing, the equalized pair, both valid bit values, and an invalid pair are tested.

Embedded simulation¶

The standalone SRAMSenseAmplifierTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMSenseAmplifier in the simulator

Source and tests¶

Test	Coverage
`SRAMSenseAmplifierTest`	The complete standalone sequence shown above

3.1.2.9. `SRAMColumnSelector<W>`¶

Routes one word's read pairs and write enables among K column groups.

IO pins¶

Pin	Direction	Width	Description
`WORD_ADDR`	Input	32	Low address bits select the word slot
`WRITE_BL_b, WRITE_BL_BAR_b, WRITE_DRIVE_b`	Input	1 each	W write-driver lanes
`BL_c, BL_BAR_c, VALID_c`	Input	1 each	Read state from all C = W*K columns
`DRIVE_c, DRIVE_BL_c, DRIVE_BL_BAR_c`	Output	1 each	Write route to each column
`READ_BL_b, READ_BL_BAR_b, READ_VALID_b`	Output	1 each	W selected read pairs

Behavior¶

The slot is WORD_ADDR % K. For lane b, the selected column is slot*W + b; this implementation uses contiguous word groups. The selector routes W read pairs and enables only that slot's write drivers. A real layout may interleave columns differently; that placement detail is not modeled here.

C++ example¶

#include <cstddef>
#include <cstdint>
#include <vector>
struct SRAMColumnReference {
    std::vector<std::optional<bool>> read_bl, read_bar, drive_bl, drive_bar;
    std::vector<bool> read_valid, drive;
};
SRAMColumnReference sram_select_ref(std::uint32_t address, std::size_t width,
    std::size_t slots, const std::vector<SRAMBitlineReference>& columns,
    const std::vector<bool>& write_bl, const std::vector<bool>& write_bar,
    const std::vector<bool>& write_drive) {
    SRAMColumnReference out;
    const auto slot = address % slots;
    for (std::size_t c = 0; c < width * slots; ++c) {
        auto b = c % width;
        out.drive_bl.push_back(write_bl.at(b)); // Data broadcast, drive decoded.
        out.drive_bar.push_back(write_bar.at(b));
        out.drive.push_back(c / width == slot && write_drive.at(b));
    }
    for (std::size_t b = 0; b < width; ++b) {
        const auto& col = columns.at(slot * width + b);
        out.read_bl.push_back(col.bl); out.read_bar.push_back(col.bar);
        out.read_valid.push_back(col.valid);
    }
    return out;
}

Unknown inputs and timing¶

Unknown slot bits follow the gate/multiplexer rules. Full-address range checking belongs to the row decoder, not this selector. K = 1 uses buffered pass-through paths rather than a multiplexer tree.

Implementation¶

Structural implementation¶

A low-bit slot decoder gates write excitation. Separate mux trees select BL, BL_BAR, and VALID for each read lane. The shared selectMuxTree construction routine creates those existing trees; it does not replace them with host indexing or a post-sense word mux. Buffers carry write values to the column groups.

Examples¶

All 2 recorded rows of SRAMColumnSelectorTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`BL_0`Input · 1 bit	`BL_1`Input · 1 bit	`BL_10`Input · 1 bit	`BL_11`Input · 1 bit	`BL_12`Input · 1 bit	`BL_13`Input · 1 bit	`BL_14`Input · 1 bit	`BL_15`Input · 1 bit	`BL_2`Input · 1 bit	`BL_3`Input · 1 bit	`BL_4`Input · 1 bit	`BL_5`Input · 1 bit	`BL_6`Input · 1 bit	`BL_7`Input · 1 bit	`BL_8`Input · 1 bit	`BL_9`Input · 1 bit	`BL_BAR_0`Input · 1 bit	`BL_BAR_1`Input · 1 bit	`BL_BAR_10`Input · 1 bit	`BL_BAR_11`Input · 1 bit	`BL_BAR_12`Input · 1 bit	`BL_BAR_13`Input · 1 bit	`BL_BAR_14`Input · 1 bit	`BL_BAR_15`Input · 1 bit	`BL_BAR_2`Input · 1 bit	`BL_BAR_3`Input · 1 bit	`BL_BAR_4`Input · 1 bit	`BL_BAR_5`Input · 1 bit	`BL_BAR_6`Input · 1 bit	`BL_BAR_7`Input · 1 bit	`BL_BAR_8`Input · 1 bit	`BL_BAR_9`Input · 1 bit	`VALID_0`Input · 1 bit	`VALID_1`Input · 1 bit	`VALID_10`Input · 1 bit	`VALID_11`Input · 1 bit	`VALID_12`Input · 1 bit	`VALID_13`Input · 1 bit	`VALID_14`Input · 1 bit	`VALID_15`Input · 1 bit	`VALID_2`Input · 1 bit	`VALID_3`Input · 1 bit	`VALID_4`Input · 1 bit	`VALID_5`Input · 1 bit	`VALID_6`Input · 1 bit	`VALID_7`Input · 1 bit	`VALID_8`Input · 1 bit	`VALID_9`Input · 1 bit	`WORD_ADDR`Input · 32 bit	`WRITE_BL_0`Input · 1 bit	`WRITE_BL_1`Input · 1 bit	`WRITE_BL_2`Input · 1 bit	`WRITE_BL_3`Input · 1 bit	`WRITE_BL_4`Input · 1 bit	`WRITE_BL_5`Input · 1 bit	`WRITE_BL_6`Input · 1 bit	`WRITE_BL_7`Input · 1 bit	`WRITE_BL_BAR_0`Input · 1 bit	`WRITE_BL_BAR_1`Input · 1 bit	`WRITE_BL_BAR_2`Input · 1 bit	`WRITE_BL_BAR_3`Input · 1 bit	`WRITE_BL_BAR_4`Input · 1 bit	`WRITE_BL_BAR_5`Input · 1 bit	`WRITE_BL_BAR_6`Input · 1 bit	`WRITE_BL_BAR_7`Input · 1 bit	`WRITE_DRIVE_0`Input · 1 bit	`WRITE_DRIVE_1`Input · 1 bit	`WRITE_DRIVE_2`Input · 1 bit	`WRITE_DRIVE_3`Input · 1 bit	`WRITE_DRIVE_4`Input · 1 bit	`WRITE_DRIVE_5`Input · 1 bit	`WRITE_DRIVE_6`Input · 1 bit	`WRITE_DRIVE_7`Input · 1 bit	`DRIVE_0`Expected output · 1 bit	`DRIVE_1`Expected output · 1 bit	`DRIVE_10`Expected output · 1 bit	`DRIVE_11`Expected output · 1 bit	`DRIVE_12`Expected output · 1 bit	`DRIVE_13`Expected output · 1 bit	`DRIVE_14`Expected output · 1 bit	`DRIVE_15`Expected output · 1 bit	`DRIVE_2`Expected output · 1 bit	`DRIVE_3`Expected output · 1 bit	`DRIVE_4`Expected output · 1 bit	`DRIVE_5`Expected output · 1 bit	`DRIVE_6`Expected output · 1 bit	`DRIVE_7`Expected output · 1 bit	`DRIVE_8`Expected output · 1 bit	`DRIVE_9`Expected output · 1 bit	`DRIVE_BL_0`Expected output · 1 bit	`DRIVE_BL_1`Expected output · 1 bit	`DRIVE_BL_10`Expected output · 1 bit	`DRIVE_BL_11`Expected output · 1 bit	`DRIVE_BL_12`Expected output · 1 bit	`DRIVE_BL_13`Expected output · 1 bit	`DRIVE_BL_14`Expected output · 1 bit	`DRIVE_BL_15`Expected output · 1 bit	`DRIVE_BL_2`Expected output · 1 bit	`DRIVE_BL_3`Expected output · 1 bit	`DRIVE_BL_4`Expected output · 1 bit	`DRIVE_BL_5`Expected output · 1 bit	`DRIVE_BL_6`Expected output · 1 bit	`DRIVE_BL_7`Expected output · 1 bit	`DRIVE_BL_8`Expected output · 1 bit	`DRIVE_BL_9`Expected output · 1 bit	`DRIVE_BL_BAR_0`Expected output · 1 bit	`DRIVE_BL_BAR_1`Expected output · 1 bit	`DRIVE_BL_BAR_10`Expected output · 1 bit	`DRIVE_BL_BAR_11`Expected output · 1 bit	`DRIVE_BL_BAR_12`Expected output · 1 bit	`DRIVE_BL_BAR_13`Expected output · 1 bit	`DRIVE_BL_BAR_14`Expected output · 1 bit	`DRIVE_BL_BAR_15`Expected output · 1 bit	`DRIVE_BL_BAR_2`Expected output · 1 bit	`DRIVE_BL_BAR_3`Expected output · 1 bit	`DRIVE_BL_BAR_4`Expected output · 1 bit	`DRIVE_BL_BAR_5`Expected output · 1 bit	`DRIVE_BL_BAR_6`Expected output · 1 bit	`DRIVE_BL_BAR_7`Expected output · 1 bit	`DRIVE_BL_BAR_8`Expected output · 1 bit	`DRIVE_BL_BAR_9`Expected output · 1 bit	`READ_BL_0`Expected output · 1 bit	`READ_BL_1`Expected output · 1 bit	`READ_BL_2`Expected output · 1 bit	`READ_BL_3`Expected output · 1 bit	`READ_BL_4`Expected output · 1 bit	`READ_BL_5`Expected output · 1 bit	`READ_BL_6`Expected output · 1 bit	`READ_BL_7`Expected output · 1 bit	`READ_BL_BAR_0`Expected output · 1 bit	`READ_BL_BAR_1`Expected output · 1 bit	`READ_BL_BAR_2`Expected output · 1 bit	`READ_BL_BAR_3`Expected output · 1 bit	`READ_BL_BAR_4`Expected output · 1 bit	`READ_BL_BAR_5`Expected output · 1 bit	`READ_BL_BAR_6`Expected output · 1 bit	`READ_BL_BAR_7`Expected output · 1 bit	`READ_VALID_0`Expected output · 1 bit	`READ_VALID_1`Expected output · 1 bit	`READ_VALID_2`Expected output · 1 bit	`READ_VALID_3`Expected output · 1 bit	`READ_VALID_4`Expected output · 1 bit	`READ_VALID_5`Expected output · 1 bit	`READ_VALID_6`Expected output · 1 bit	`READ_VALID_7`Expected output · 1 bit
#0`slot-0`	4	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0x00000000`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`
#1`slot-1`	9	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0x00000001`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`0`	`1`	`1`	`1`	`1`	`1`	`1`	`1`	`1`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Two word slots contain opposite bit patterns. The example verifies every selected read lane, every write-enable route, and the complementary write values.

Embedded simulation¶

The standalone SRAMColumnSelectorTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMColumnSelector<W> in the simulator

Source and tests¶

Test	Coverage
`SRAMColumnSelectorTest`	The complete standalone sequence shown above

3.1.2.10. `SRAMAccessControl<W>`¶

Timed digital primitive sequencing an asynchronous access.

IO pins¶

Pin	Direction	Width	Description
`WORD_ADDR`	Input	32	Requested word index
`WRITE_DATA`	Input	W	Write data
`WRITE_MASK`	Input	W/8	Byte write enables
`CE_N, WE_N, OE_N`	Input	1 each	Active-low chip, write, and output enables
`ADDRESS, DATA, MASK`	Output	32, W, W/8	Staged address and write signals
`PRECHARGE, ROW_ENABLE, WRITE_ENABLE, SENSE_ENABLE, OUTPUT_ENABLE`	Output	1 each	Internal phase controls

Behavior¶

A selected operation follows the timing sequence described above. Address changes, CE/WE changes, and write data/mask changes during a write restart it safely. Old address/data remain staged while the previous row is being disabled. OE only gates the completed read output; it does not restart the access. Write data/mask changes during a read are ignored.

Queued timer events recheck the current deadline and phase. Canceling or replacing a request prevents an old timer from completing that previous request.

C++ example¶

#include <cstddef>
#include <cstdint>
#include <optional>
#include <tuple>
struct SRAMControlReference {
    enum class Phase { Idle, Quiet, Precharge, Release, Access, Ready };
    Phase phase = Phase::Idle;
    struct Inputs {
        std::uint32_t address = 0, data = 0;
        unsigned mask = 0;
        bool ce_n = true, we_n = true, oe_n = true;
    };
    using Signature = std::tuple<std::uint32_t, bool, bool, std::uint32_t, unsigned>;
    std::optional<Signature> signature;
    Inputs pending;
    std::size_t due = 0;
    std::uint32_t address = 0, data = 0;
    unsigned mask = 0;
    bool precharge = false, row_enable = false, write_enable = false;
    bool sense_enable = false, output_enable = false;
    void update(std::size_t now, std::size_t ticks, const Inputs& in) {
        Signature next{in.address, in.ce_n, in.we_n,
                       in.we_n ? 0 : in.data, in.we_n ? 0 : in.mask};
        if (signature != next) { // OE and read-mode write buses do not restart.
            signature = next; pending = in;
            precharge = row_enable = write_enable = sense_enable = false;
            phase = in.ce_n ? Phase::Idle : Phase::Quiet;
            due = in.ce_n ? 0 : now + ticks;
        } else if (due && now >= due) {
            switch (phase) {
            case Phase::Quiet:
                address = pending.address; data = pending.data; mask = pending.mask;
                precharge = true; phase = Phase::Precharge; break;
            case Phase::Precharge:
                precharge = false; write_enable = !pending.we_n;
                phase = Phase::Release; break;
            case Phase::Release: row_enable = true; phase = Phase::Access; break;
            case Phase::Access: sense_enable = pending.we_n; phase = Phase::Ready; break;
            default: break;
            }
            due = phase == Phase::Ready ? 0 : now + ticks;
        }
        output_enable = phase == Phase::Ready && !in.ce_n && in.we_n && !in.oe_n;
    }
};

Unknown inputs and timing¶

Call update on input changes and at every nonzero due; a superseded deadline is harmless because the current request owns due. Inputs changing exactly at a deadline restart the access before that old phase can advance. Unknown CE/WE suppress operation; unknown OE disables output. Unknown addresses are passed through and handled by the row/bitline circuitry. The example assumes binary inputs and valid positive ticks. This is a conservative digital timing contract, not a specific vendor's timing model.

Implementation¶

Structural implementation¶

A registered terminal timing primitive implemented by AccessSequence. It schedules future evaluations in the existing simulator. No global clock, wire change, or new engine event type is required.

Examples¶

All 5 recorded rows of SRAMAccessControlTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`CE_N`Input · 1 bit	`OE_N`Input · 1 bit	`WE_N`Input · 1 bit	`WORD_ADDR`Input · 32 bit	`WRITE_DATA`Input · 8 bit	`WRITE_MASK`Input · 1 bit	`ADDRESS`Expected output · 32 bit	`DATA`Expected output · 8 bit	`MASK`Expected output · 1 bit	`OUTPUT_ENABLE`Expected output · 1 bit	`PRECHARGE`Expected output · 1 bit	`ROW_ENABLE`Expected output · 1 bit	`SENSE_ENABLE`Expected output · 1 bit	`WRITE_ENABLE`Expected output · 1 bit
#0`deselected`	0	`1`	`0`	`1`	`0x00000001`	`0xA5`	`1`	not checked	not checked	not checked	`0`	not checked	`0`	not checked	not checked
#1`read-complete`	129	`0`	`0`	`1`	`0x00000001`	`0xA5`	`1`	`0x00000001`	not checked	not checked	`1`	`0`	`1`	`1`	`0`
#2`output-disabled`	130	`0`	`1`	`1`	`0x00000001`	`0xA5`	`1`	not checked	not checked	not checked	`0`	not checked	`1`	not checked	not checked
#3`write-complete`	259	`0`	`1`	`0`	`0x00000001`	`0xA5`	`1`	not checked	`0xA5`	`1`	`0`	not checked	not checked	`0`	`1`
#4`deselect`	260	`1`	`1`	`0`	`0x00000001`	`0xA5`	`1`	not checked	not checked	not checked	not checked	`0`	`0`	not checked	`0`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The standalone checkpoints show deselection, completed read, OE-only disable, completed write, and deselection. Intermediate precharge/release/access phases remain visible on the timeline. SRAMTimingTest additionally checks partial accesses and stale timers.

Embedded simulation¶

The standalone SRAMAccessControlTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMAccessControl<W> in the simulator

Source and tests¶

Test	Coverage
`SRAMAccessControlTest`	The complete standalone sequence shown above
`SRAMTimingTest`	Canceled short writes, incomplete reads, superseded address requests, and eventual event-queue quiescence

3.1.2.11. `SRAMOutputBuffer<W>`¶

Digital output-enable primitive with high-impedance disabled output.

IO pins¶

Pin	Direction	Width	Description
`DATA`	Input	W	Read word from sense amplifiers
`ENABLE`	Input	1	Present read data
`OUT`	Output	W	Data when enabled, Z when disabled

Behavior¶

A high enable forwards the input word. A low enable produces Z on every output bit. This models an output driver being disabled; it does not make the simulator wire bidirectional or resolve other drivers.

C++ example¶

#include <cstdint>
#include <optional>
std::optional<std::uint32_t> sram_output_ref(std::uint32_t data, bool enable) {
    if (enable) return data;
    return std::nullopt; // Disabled output, not a stored zero.
}

Unknown inputs and timing¶

An unknown/Z enable produces X rather than choosing between driving and disconnecting. Enabled data preserves its four-state values. Output delay is one tick.

Implementation¶

Structural implementation¶

A compatibility wrapper inheriting the common MemoryOutputBuffer implementation. It retains the SRAM catalog ID, display name, pins, and one-tick delay without adding a child component. The implementation is a terminal digital primitive because ordinary Boolean gates cannot produce the required Z output. There is no separate behavioral replacement.

Examples¶

All 4 recorded rows of SRAMOutputBufferTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`DATA`Input · 8 bit	`ENABLE`Input · 1 bit	`OUT`Expected output · 8 bit
#0`disabled`	1	`0xA5`	`0`	`0bZZZZZZZZ`
#1`enabled`	3	`0xA5`	`1`	`0xA5`
#2`unknown-enable`	5	`0xA5`	`X`	`0bXXXXXXXX`
#3`disable-again`	7	`0xA5`	`0`	`0bZZZZZZZZ`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

The example checks disabled Z, enabled data, unknown enable, and returning to disabled Z.

Embedded simulation¶

The standalone SRAMOutputBufferTest opens this component as SRAM_ROOT. Expand the component where it has structural children; a terminal digital primitive is intentionally a leaf.

Open SRAMOutputBuffer<W> in the simulator

Source and tests¶

Test	Coverage
`SRAMOutputBufferTest`	The complete standalone sequence shown above

3.1.2.12. `SRAM<W>`¶

Complete word-addressed asynchronous SRAM device.

IO pins¶

Pin	Direction	Width	Description
`WORD_ADDR`	Input	32	Word index, not byte address
`WRITE_DATA`	Input	W	Data for the selected word
`WRITE_MASK`	Input	W/8	Bit b enables byte b; bit 0 is the least-significant byte
`CE_N`	Input	1	Low selects the device
`WE_N`	Input	1	Low requests writing; high requests reading
`OE_N`	Input	1	Low enables a completed read output
`READ_DATA`	Output	W	Read result, or Z while disabled/writing/accessing

Behavior¶

CE_N = 1 disables access without clearing memory. With CE_N = 0, WE_N = 0 writes the enabled bytes after the access phases; WE_N = 1 reads. OE controls only read output. A zero write mask changes no bits. Reads are nondestructive. There is no clock, reset, refresh command, READY handshake, or hardware FAULT pin.

A known out-of-range read returns X after access; an out-of-range write changes no cells. Unknown address/control handling is a simulator rule, not a hardware exception mechanism. Use the SRAM-specific memory controller to connect this native port to the shared transaction protocol.

C++ example¶

#include <cstddef>
#include <cstdint>
#include <optional>
#include <vector>
template<std::size_t W> struct SRAMReference {
    static_assert(W == 8 || W == 16 || W == 32);
    using Word = std::vector<std::optional<bool>>;
    std::vector<Word> words;
    SRAMControlReference control;
    Word read_data = Word(W);
    bool high_z = true;
    explicit SRAMReference(std::size_t count) : words(count, Word(W)) {}
    void update(std::size_t now, std::size_t ticks, const SRAMControlReference::Inputs& in) {
        const auto previous = control.phase;
        control.update(now, ticks, in);
        const bool valid = control.address < words.size();
        if (previous == SRAMControlReference::Phase::Release &&
            control.phase == SRAMControlReference::Phase::Access && control.write_enable && valid) {
            for (unsigned b = 0; b < W; ++b)
                if (control.mask & (1u << (b / 8)))
                    words[control.address][b] = bool((control.data >> b) & 1u);
        }
        high_z = !control.output_enable;
        read_data = !high_z && valid ? words[control.address] : Word(W);
    }
};

Unknown inputs and timing¶

The example includes unknown startup, partial initialization, byte masks, output disable, invalid addresses, request cancellation, and access deadlines. high_z distinguishes a disabled output from an enabled unknown word. Its inputs are binary and geometry is prevalidated; unknown write data additionally makes only enabled bits unknown, and unknown byte enables suppress writes to those lanes. Call at input changes and every control.due. Gate propagation is omitted; use at least 4*phase_ticks + 32 ticks for a conservative simulator settling budget.

Implementation¶

Structural implementation¶

Combines ACCESS_CONTROL, ROW_DECODE, PRECHARGE, STORAGE, COLUMN_SELECT, W WRITE_DRIVER_b and SENSE_b instances, bus wiring, and OUTPUT. Each SRAMWriteDriver retains its own write-enable/mask gate and complementary data pair: the drive and bitline paths must keep their tested relative timing. Precharge control and repeated column-select complements are shared, while each bitline pair and sense amplifier remains visible. The device expands at most 4096 cells. The default 4×8 example has two rows, 16 bitline pairs, and 32 cells.

Behavioral implementation¶

The same access sequencer controls a packed, optionally paged MemoryStorage. It preserves native pins and unknown startup without expanding rows/cells. Capacity is bounded by 32-bit byte addressing and explicit allocation/history budgets. Setup image loading is allowed only before simulation starts. Selecting behavioral fidelity at STORAGE instead retains the complete device's visible peripheral circuitry and its small-bank geometry limit.

Examples¶

All 35 recorded rows of SRAMTest, in checkpoint order. Outputs are test expectations verified against the simulation. Time is the absolute settled checkpoint time in simulator units, not milliseconds or CPU cycles.

Default scenario profile: canonical-default-preview / structural (59857f039337ca4c). Changing fidelity or the circuit can change these times.

Checkpointzero-based number · timeline label	Timesimulator units	`CE_N`Input · 1 bit	`OE_N`Input · 1 bit	`WE_N`Input · 1 bit	`WORD_ADDR`Input · 32 bit	`WRITE_DATA`Input · 8 bit	`WRITE_MASK`Input · 1 bit	`READ_DATA`Expected output · 8 bit
#0`deselected-startup`	5	`1`	`0`	`1`	`0x00000000`	`0x00`	`1`	`0bZZZZZZZZ`
#1`unwritten-read`	135	`0`	`0`	`1`	`0x00000000`	`0x00`	`1`	`0bXXXXXXXX`
#2`setup-word-0`	139	`1`	`0`	`1`	`0x00000000`	`0x81`	`1`	`0bZZZZZZZZ`
#3`write-word-0`	268	`0`	`0`	`0`	`0x00000000`	`0x81`	`1`	`0bZZZZZZZZ`
#4`read-word-0`	399	`0`	`0`	`1`	`0x00000000`	`0x81`	`1`	`0x81`
#5`setup-word-1`	406	`1`	`0`	`1`	`0x00000001`	`0xE6`	`1`	`0bZZZZZZZZ`
#6`write-word-1`	535	`0`	`0`	`0`	`0x00000001`	`0xE6`	`1`	`0bZZZZZZZZ`
#7`read-word-1`	666	`0`	`0`	`1`	`0x00000001`	`0xE6`	`1`	`0xE6`
#8`setup-word-2`	673	`1`	`0`	`1`	`0x00000002`	`0x4F`	`1`	`0bZZZZZZZZ`
#9`write-word-2`	802	`0`	`0`	`0`	`0x00000002`	`0x4F`	`1`	`0bZZZZZZZZ`
#10`read-word-2`	933	`0`	`0`	`1`	`0x00000002`	`0x4F`	`1`	`0x4F`
#11`setup-word-3`	940	`1`	`0`	`1`	`0x00000003`	`0xB4`	`1`	`0bZZZZZZZZ`
#12`write-word-3`	1069	`0`	`0`	`0`	`0x00000003`	`0xB4`	`1`	`0bZZZZZZZZ`
#13`read-word-3`	1200	`0`	`0`	`1`	`0x00000003`	`0xB4`	`1`	`0xB4`
#14`mask-setup-0`	1207	`1`	`0`	`1`	`0x00000000`	`0x10`	`0`	`0bZZZZZZZZ`
#15`masked-write-0`	1336	`0`	`0`	`0`	`0x00000000`	`0x10`	`0`	`0bZZZZZZZZ`
#16`masked-read-0`	1467	`0`	`0`	`1`	`0x00000000`	`0x10`	`0`	`0x81`
#17`mask-setup-1`	1474	`1`	`0`	`1`	`0x00000001`	`0x55`	`1`	`0bZZZZZZZZ`
#18`masked-write-1`	1603	`0`	`0`	`0`	`0x00000001`	`0x55`	`1`	`0bZZZZZZZZ`
#19`masked-read-1`	1734	`0`	`0`	`1`	`0x00000001`	`0x55`	`1`	`0x55`
#20`disable-output`	1736	`0`	`1`	`1`	`0x00000001`	`0x55`	`1`	`0bZZZZZZZZ`
#21`read-last-word`	1867	`0`	`0`	`1`	`0x00000003`	`0x55`	`1`	`0xB4`
#22`ignored-write-inputs-during-read`	1868	`0`	`0`	`1`	`0x00000003`	`0bXXXXXXXX`	`X`	`0xB4`
#23`invalid-read`	1998	`0`	`0`	`1`	`0x00000004`	`0bXXXXXXXX`	`X`	`0bXXXXXXXX`
#24`invalid-write`	2127	`0`	`0`	`0`	`0x00000004`	`0x00`	`1`	`0bZZZZZZZZ`
#25`end-invalid-write`	2132	`1`	`0`	`1`	`0x00000004`	`0x00`	`1`	`0bZZZZZZZZ`
#26`readback-0`	2263	`0`	`0`	`1`	`0x00000000`	`0x00`	`1`	`0x81`
#27`readback-1`	2394	`0`	`0`	`1`	`0x00000001`	`0x00`	`1`	`0x55`
#28`readback-2`	2525	`0`	`0`	`1`	`0x00000002`	`0x00`	`1`	`0x4F`
#29`readback-3`	2656	`0`	`0`	`1`	`0x00000003`	`0x00`	`1`	`0xB4`
#30`prepare-unknown-write`	2663	`1`	`0`	`1`	`0x00000000`	`0bXXXXXXXX`	`1`	`0bZZZZZZZZ`
#31`write-unknown`	2792	`0`	`0`	`0`	`0x00000000`	`0bXXXXXXXX`	`1`	`0bZZZZZZZZ`
#32`read-unknown`	2922	`0`	`0`	`1`	`0x00000000`	`0bXXXXXXXX`	`1`	`0bXXXXXXXX`
#33`unknown-address`	3052	`0`	`0`	`1`	`0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX`	`0bXXXXXXXX`	`1`	`0bXXXXXXXX`
#34`deselect-retains`	3056	`1`	`0`	`1`	`0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX`	`0bXXXXXXXX`	`1`	`0bZZZZZZZZ`

Scroll within the table for all rows and pins. Buses use hexadecimal; values containing X/Z use MSB-first binary. Inputs show the declared values in effect at each checkpoint, including retained inputs. Sequential tests also replay preparation changes between checkpoints, such as lowering the clock. Use the matching checkpoint label in the simulation below.

Every recorded row is included: unknown startup, all four addresses, both 8-bit masks, OE disable, ignored read-mode write inputs, invalid accesses, retention readback, unknown writes, and unknown addressing. Wider 16/32-bit masks and other geometries are covered by the contract test.

Embedded simulation¶

The standalone SRAMTest opens this component as SRAM_ROOT. Use the explorer to compare structural and behavioral fidelity.

Open SRAM<W> in the simulator

Source and tests¶

Test	Coverage
`SRAMTest`	The complete standalone sequence shown above
`SRAMContractTest`	Structural/behavioral equivalence; device and bank widths 8/16/32, multiple geometries and byte masks, mixed bank selection, and invalid configuration rejection
`SRAMTimingTest`	Canceled short writes, incomplete reads, superseded address requests, and eventual event-queue quiescence
`DocumentationExamplesTest`	Compile the exact page snippets; exercise cell/bitline conflicts, bank reads/writes, column routing, masks, cancellation, and deadlines; replay the device scenario's uninterrupted binary-input prefix against recorded outputs

§ 3.1.2. SRAM¶

Geometry and interface conventions¶

Construction¶

Access timing¶

3.1.2.1. SRAMCell¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Behavioral implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.2. SRAMRow¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Behavioral implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.3. SRAMBitlinePair¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.4. SRAMStorageBank<W>¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Behavioral implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.5. SRAMRowDecoder¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.6. SRAMPrecharge¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.7. SRAMWriteDriver¶

IO pins¶

Behavior¶

C++ example¶

Unknown inputs and timing¶

Implementation¶

Structural implementation¶

Examples¶

Embedded simulation¶

Source and tests¶

3.1.2.8. SRAMSenseAmplifier¶

IO pins¶

Behavior¶

3.1.2.1. `SRAMCell`¶

3.1.2.2. `SRAMRow`¶

3.1.2.3. `SRAMBitlinePair`¶

3.1.2.4. `SRAMStorageBank<W>`¶

3.1.2.5. `SRAMRowDecoder`¶

3.1.2.6. `SRAMPrecharge`¶

3.1.2.7. `SRAMWriteDriver`¶

3.1.2.8. `SRAMSenseAmplifier`¶

3.1.2.9. `SRAMColumnSelector<W>`¶

3.1.2.10. `SRAMAccessControl<W>`¶

3.1.2.11. `SRAMOutputBuffer<W>`¶

3.1.2.12. `SRAM<W>`¶